ASoC: da732x: simplify code
authorPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Fri, 26 Mar 2021 22:16:19 +0000 (17:16 -0500)
committerMark Brown <broonie@kernel.org>
Wed, 31 Mar 2021 17:00:38 +0000 (18:00 +0100)
cppcheck reports a false positive:

sound/soc/codecs/da732x.c:1161:25: warning: Either the condition
'indiv<0' is redundant or there is division by zero at line
1161. [zerodivcond]
 fref = (da732x->sysclk / indiv);
                        ^
sound/soc/codecs/da732x.c:1158:12: note: Assuming that condition
'indiv<0' is not redundant
 if (indiv < 0)
           ^
sound/soc/codecs/da732x.c:1161:25: note: Division by zero
 fref = (da732x->sysclk / indiv);
                        ^

The code is awfully convoluted/confusing and can be simplified with a
single variable and the BIT macro.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20210326221619.949961-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/da732x.c
sound/soc/codecs/da732x.h

index d43ee71..42d6a3f 100644 (file)
@@ -168,30 +168,25 @@ static const struct reg_default da732x_reg_cache[] = {
 static inline int da732x_get_input_div(struct snd_soc_component *component, int sysclk)
 {
        int val;
-       int ret;
 
        if (sysclk < DA732X_MCLK_10MHZ) {
-               val = DA732X_MCLK_RET_0_10MHZ;
-               ret = DA732X_MCLK_VAL_0_10MHZ;
+               val = DA732X_MCLK_VAL_0_10MHZ;
        } else if ((sysclk >= DA732X_MCLK_10MHZ) &&
            (sysclk < DA732X_MCLK_20MHZ)) {
-               val = DA732X_MCLK_RET_10_20MHZ;
-               ret = DA732X_MCLK_VAL_10_20MHZ;
+               val = DA732X_MCLK_VAL_10_20MHZ;
        } else if ((sysclk >= DA732X_MCLK_20MHZ) &&
            (sysclk < DA732X_MCLK_40MHZ)) {
-               val = DA732X_MCLK_RET_20_40MHZ;
-               ret = DA732X_MCLK_VAL_20_40MHZ;
+               val = DA732X_MCLK_VAL_20_40MHZ;
        } else if ((sysclk >= DA732X_MCLK_40MHZ) &&
            (sysclk <= DA732X_MCLK_54MHZ)) {
-               val = DA732X_MCLK_RET_40_54MHZ;
-               ret = DA732X_MCLK_VAL_40_54MHZ;
+               val = DA732X_MCLK_VAL_40_54MHZ;
        } else {
                return -EINVAL;
        }
 
        snd_soc_component_write(component, DA732X_REG_PLL_CTRL, val);
 
-       return ret;
+       return val;
 }
 
 static void da732x_set_charge_pump(struct snd_soc_component *component, int state)
@@ -1158,7 +1153,7 @@ static int da732x_set_dai_pll(struct snd_soc_component *component, int pll_id,
        if (indiv < 0)
                return indiv;
 
-       fref = (da732x->sysclk / indiv);
+       fref = da732x->sysclk / BIT(indiv);
        div_hi = freq_out / fref;
        frac_div = (u64)(freq_out % fref) * 8192ULL;
        do_div(frac_div, fref);
index c5af17e..c2f784c 100644 (file)
 #define        DA732X_MCLK_20MHZ               20000000
 #define        DA732X_MCLK_40MHZ               40000000
 #define        DA732X_MCLK_54MHZ               54000000
-#define        DA732X_MCLK_RET_0_10MHZ         0
-#define        DA732X_MCLK_VAL_0_10MHZ         1
-#define        DA732X_MCLK_RET_10_20MHZ        1
-#define        DA732X_MCLK_VAL_10_20MHZ        2
-#define        DA732X_MCLK_RET_20_40MHZ        2
-#define        DA732X_MCLK_VAL_20_40MHZ        4
-#define        DA732X_MCLK_RET_40_54MHZ        3
-#define        DA732X_MCLK_VAL_40_54MHZ        8
+#define        DA732X_MCLK_VAL_0_10MHZ         0
+#define        DA732X_MCLK_VAL_10_20MHZ        1
+#define        DA732X_MCLK_VAL_20_40MHZ        2
+#define        DA732X_MCLK_VAL_40_54MHZ        3
 #define        DA732X_DAI_ID1                  0
 #define        DA732X_DAI_ID2                  1
 #define        DA732X_SRCCLK_PLL               0