pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug
24, 2018, the MOD_SEL0 bit16 must be set to 0 when the NFALE_A and
NFRB_N_A pin functions are selected.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index ebf4d5e..2328fd2 100644 (file)
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1038,7 +1038,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP10_23_20,            NFCLE),
 
        PINMUX_IPSR_GPSR(IP10_27_24,            SD0_CD),
-       PINMUX_IPSR_GPSR(IP10_27_24,            NFALE_A),
+       PINMUX_IPSR_MSEL(IP10_27_24,            NFALE_A,        SEL_NDFC_0),
        PINMUX_IPSR_GPSR(IP10_27_24,            SD3_CD),
        PINMUX_IPSR_MSEL(IP10_27_24,            RIF0_CLK_B,     SEL_DRIF0_1),
        PINMUX_IPSR_MSEL(IP10_27_24,            SCL2_B,         SEL_I2C2_1),
@@ -1047,7 +1047,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP10_27_24,            TS_SCK0),
 
        PINMUX_IPSR_GPSR(IP10_31_28,            SD0_WP),
-       PINMUX_IPSR_GPSR(IP10_31_28,            NFRB_N_A),
+       PINMUX_IPSR_MSEL(IP10_31_28,            NFRB_N_A,       SEL_NDFC_0),
        PINMUX_IPSR_GPSR(IP10_31_28,            SD3_WP),
        PINMUX_IPSR_MSEL(IP10_31_28,            RIF0_D0_B,      SEL_DRIF0_1),
        PINMUX_IPSR_MSEL(IP10_31_28,            SDA2_B,         SEL_I2C2_1),