.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_names = gcc_parent_names_ao_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_ao_0),
.flags = CLK_IS_CRITICAL,
.ops = &clk_rcg2_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup0_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup0_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart0_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup0_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup0_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart0_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_names = gcc_parent_names_5,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "emac_clk_src",
.parent_names = gcc_parent_names_4,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_4),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "emac_ptp_clk_src",
.parent_names = gcc_parent_names_4,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_4),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_names = gcc_parent_names_6,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_6),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_names = gcc_parent_names_7,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_7),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_names = gcc_parent_names_2,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_2),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_names = gcc_parent_names_2,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_2),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_names = gcc_parent_names_2,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_2),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_app_clk_src",
.parent_names = gcc_parent_names_1,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_1),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_pclk_clk_src",
.parent_names = gcc_parent_names_8,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_8),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_names = gcc_parent_names_9,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_9),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_aux_clk_src",
.parent_names = gcc_parent_names_10,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_10),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_pipe_clk_src",
.parent_names = gcc_parent_names_11,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_11),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_names = gcc_parent_names_12,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_12),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_names = gcc_parent_names_13,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_13),
.ops = &clk_rcg2_floor_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
.parent_names = gcc_parent_names_3,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_3),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_names = gcc_parent_names_14,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_14),
.ops = &clk_rcg2_floor_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "usb20_mock_utmi_clk_src",
.parent_names = gcc_parent_names_1,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_1),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_names = gcc_parent_names_1,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_1),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "usb3_phy_aux_clk_src",
.parent_names = gcc_parent_names_1,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_1),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_names = gcc_parent_names_3,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_3),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_names = gcc_parent_names_15,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_15),
.ops = &clk_rcg2_ops,
},
};
.clkr.hw.init = &(struct clk_init_data) {
.name = "cdsp_bimc_clk_src",
.parent_names = gcc_parent_names_16,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_16),
.ops = &clk_rcg2_ops,
},
};