TPL: TM2: set MAX77843 MUIC to USB path before entering download mode

Use simple soft i2c gpio bit-bang based controller to enable MUIC register
write.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I4087fe304d49bd4b88657e6bb4f0bd438e92d6d3

diff --git a/arch/arm/include/asm/arch-exynos5433/gpio.h b/arch/arm/include/asm/arch-exynos5433/gpio.h
deleted file mode 120000 (symlink)
index a5e2c3d9846aaf037c0e623045e62993f75bf5ae..0000000000000000000000000000000000000000
--- a/arch/arm/include/asm/arch-exynos5433/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-../../../mach-exynos/include/mach/gpio.h
\ No newline at end of file

diff --git a/arch/arm/include/asm/arch-exynos5433/gpio.h b/arch/arm/include/asm/arch-exynos5433/gpio.h
new file mode 100644 (file)
index 0000000000000000000000000000000000000000..85624c916e7115ff991b3496d0f2ed746e433fbf
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos5433/gpio.h
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2016 Samsung Electronics
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/io.h>
+
+/* hsi2c_8 */
+/* Pins gpb0-1 gpb0-0 */
+
+#define GPIO_GPB0_BASE 0x14CC0020
+#define GPIO_I2C_SDA_PIN 0
+#define GPIO_I2C_SCL_PIN 1
+
+#define GPB0_CON 0x00
+#define GPB0_DAT 0x04
+#define GPB0_PUD 0x08
+#define GPB0_DRV 0x0C
+#define GPB0_CONPDN 0x10
+#define GPB0_PUDPDN 0x14
+
+#define CON_MASK(val)                  (0xf << ((val) << 2))
+#define CON_SFR(gpio, cfg)             ((cfg) << ((gpio) << 2))
+
+#define DAT_MASK(gpio)                 (0x1 << (gpio))
+#define DAT_SET(gpio)                  (0x1 << (gpio))
+
+#define PULL_MASK(gpio)                (0x3 << ((gpio) << 1))
+#define PULL_MODE(gpio, pull)          ((pull) << ((gpio) << 1))
+
+#define DRV_MASK(gpio)                 (0x3 << ((gpio) << 1))
+#define DRV_SET(gpio, mode)            ((mode) << ((gpio) << 1))
+
+/* Pin configurations */
+#define S5P_GPIO_INPUT 0x0
+#define S5P_GPIO_OUTPUT        0x1
+#define S5P_GPIO_IRQ   0xf
+#define S5P_GPIO_FUNC(x)       (x)
+
+/* Pull mode */
+#define S5P_GPIO_PULL_NONE     0x0
+#define S5P_GPIO_PULL_DOWN     0x1
+#define S5P_GPIO_PULL_UP       0x3
+
+/* Drive Strength level */
+#define S5P_GPIO_DRV_1X        0x0
+#define S5P_GPIO_DRV_3X        0x1
+#define S5P_GPIO_DRV_2X        0x2
+#define S5P_GPIO_DRV_4X        0x3
+#define S5P_GPIO_DRV_FAST      0x0
+#define S5P_GPIO_DRV_SLOW      0x1
+
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+       debug("%s: GPIO: %d -> %s\n", __func__, gpio, label);
+       return 0;
+}
+
+static inline int gpio_free(unsigned gpio)
+{
+       debug("%s: GPIO: %d\n", __func__, gpio);
+       return 0;
+}
+
+static inline void gpio_set_pin_value(void *addr, unsigned gpio, int en)
+{
+       unsigned int value;
+
+       value = readl(addr);
+       value &= ~DAT_MASK(gpio);
+       if (en)
+               value |= DAT_SET(gpio);
+       writel(value, addr);
+}
+
+static inline void gpio_cfg_pin(void *addr, unsigned gpio, int cfg)
+{
+       unsigned int value;
+
+       value = readl(addr);
+       value &= ~CON_MASK(gpio);
+       value |= CON_SFR(gpio, cfg);
+       writel(value, addr);
+
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+       void *base = (void*) GPIO_GPB0_BASE;
+
+       debug("%s: GPIO: %d\n", __func__, gpio);
+
+       gpio_cfg_pin(base + GPB0_CON, gpio, S5P_GPIO_INPUT);
+
+       return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+       void *base = (void*) GPIO_GPB0_BASE;
+
+       debug("%s: GPIO: %d VAL: %d\n", __func__, gpio, value);
+
+       gpio_set_pin_value(base + GPB0_DAT, gpio, value);
+       gpio_cfg_pin(base + GPB0_CON, gpio, S5P_GPIO_OUTPUT);
+
+       return 0;
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+       void *base = (void*) GPIO_GPB0_BASE;
+       unsigned int value;
+
+       debug("%s: GPIO: %d\n", __func__, gpio);
+
+       value = readl(base + GPB0_DAT);
+       return !!(value & DAT_MASK(gpio));
+}
+
+static inline int gpio_set_value(unsigned gpio, int value)
+{
+       void *base = (void*) GPIO_GPB0_BASE;
+
+       debug("%s: GPIO: %d VAL: %d\n", __func__, gpio, value);
+
+       gpio_set_pin_value(base + GPB0_DAT, gpio, value);
+
+       return 0;
+}
+
+static inline void gpio_set_pull(int gpio, int mode)
+{
+       void *base = (void*) GPIO_GPB0_BASE;
+       unsigned int value;
+
+       value = readl(base + GPB0_PUD);
+       value &= ~PULL_MASK(gpio);
+
+       switch (mode) {
+       case S5P_GPIO_PULL_DOWN:
+       case S5P_GPIO_PULL_UP:
+               value |= PULL_MODE(gpio, mode);
+               break;
+       default:
+               break;
+       }
+
+       writel(value, base + GPB0_PUD);
+}
+
+static inline void gpio_set_drv(int gpio, int mode)
+{
+       void *base = (void*) GPIO_GPB0_BASE;
+       unsigned int value;
+
+       value = readl(base + GPB0_DRV);
+       value &= ~DRV_MASK(gpio);
+
+       switch (mode) {
+       case S5P_GPIO_DRV_1X:
+       case S5P_GPIO_DRV_2X:
+       case S5P_GPIO_DRV_3X:
+       case S5P_GPIO_DRV_4X:
+               value |= DRV_SET(gpio, mode);
+               break;
+       default:
+               return;
+       }
+
+       writel(value, base + GPB0_DRV);
+}
+
+#endif
+#endif

diff --git a/board/samsung/tm2/tm2.c b/board/samsung/tm2/tm2.c
index cd63f88..757dc5d 100644 (file)
--- a/board/samsung/tm2/tm2.c
+++ b/board/samsung/tm2/tm2.c
@@ -15,6 +15,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/power.h>
 #include <samsung-usb-phy-uboot.h>
+#include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -104,6 +105,23 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+void i2c_init_board(void)
+{
+       /* Soft I2C - hsi2c_8 */
+
+       gpio_request(GPIO_I2C_SDA_PIN, "hsi2c_8_data");
+       gpio_request(GPIO_I2C_SCL_PIN, "hsi2c_8_clk");
+       gpio_direction_output(GPIO_I2C_SDA_PIN, 1);
+       gpio_direction_output(GPIO_I2C_SCL_PIN, 1);
+
+       gpio_set_pull(GPIO_I2C_SCL_PIN, S5P_GPIO_PULL_UP);
+       gpio_set_pull(GPIO_I2C_SDA_PIN, S5P_GPIO_PULL_UP);
+
+       gpio_set_drv(GPIO_I2C_SCL_PIN, S5P_GPIO_DRV_1X);
+       gpio_set_drv(GPIO_I2C_SDA_PIN, S5P_GPIO_DRV_1X);
+}
+#endif
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
        .maximum_speed = USB_SPEED_SUPER,

diff --git a/include/configs/tm2.h b/include/configs/tm2.h
index 7836012..3405896 100644 (file)
--- a/include/configs/tm2.h
+++ b/include/configs/tm2.h
@@ -62,6 +62,17 @@
 #define CONFIG_G_DNL_UMS_VENDOR_NUM    CONFIG_G_DNL_VENDOR_NUM
 #define CONFIG_G_DNL_UMS_PRODUCT_NUM   0xA4A5
 
+/* I2C */
+#define CONFIG_SOFT_I2C_GPIO_SCL       GPIO_I2C_SCL_PIN
+#define CONFIG_SOFT_I2C_GPIO_SDA       GPIO_I2C_SDA_PIN
+
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED      50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE      0x00
+#define CONFIG_SYS_I2C_INIT_BOARD
+
 /* CONFIG_SYS_TEXT_BASE needs to align with where sboot loads kernel */
 #define CONFIG_SYS_TEXT_BASE           0x20080000
 
@@ -86,12 +97,15 @@
 /* Initial environment variables */
 #define CONFIG_BOOTCOMMAND             "run modedetect"
 #define CONFIG_EXTRA_ENV_SETTINGS      "dfu_alt_info=kernel part 0 9 offset 0x400;rootfs part 0 18;system-data part 0 19;user part 0 21\0" \
-                                       "modedetect=if itest.l *0x10580044 == 0x81 || itest.l *0x10580044 == 0x1 || itest.l *0x105c080c == 0x12345671; then echo Thor mode enabled; run displayimg; mw.l 0x105c080c 0; thor 0 mmc 0; reset; else echo Booting kernel; run boarddetect; run loadkernel; bootm 0x30080000#$board; reset; fi\0" \
+                                       "modedetect=if itest.l *0x10580044 == 0x81 || itest.l *0x10580044 == 0x1 || itest.l *0x105c080c == 0x12345671; then run download; else run bootkernel; fi; reset\0" \
                                        "fdt_high=0xffffffffffffffff\0" \
                                        "bootargs=console=ttySAC1,115200 earlycon=exynos4210,0x14C20000 loglevel=7 root=/dev/mmcblk0p18 rootfstype=ext4 rootwait\0" \
+                                       "bootkernel=echo Booting kernel; run boarddetect; run loadkernel; bootm 0x30080000#$board\0" \
                                        "boarddetect=if itest.l *0x138000b4 == 0x0063f9ff; then setenv board tm2e; elif itest.l *0x138000b4 == 0x0059f9ff; then setenv board tm2; else setenv board unknown; fi; echo Detected $board board\0" \
                                        "loadkernel=part start mmc 0 9 kernel_sect; part size mmc 0 9 kernel_size; mmc read 0x30000000 $kernel_sect $kernel_size\0" \
-                                       "displayimg=unzip 200d0000 67000000; mw.l 138000b4 0059f9ff; mw.l 138001a0 67e10000; mw.l 13800200 00001680; mw.l 13801410 1; mw.l 13802040 e0000018; sleep 1; mw.l 13802040 e0000008\0"
+                                       "muicsetusb=i2c mw 25 c 1b; i2c mw 25 d 3b; i2c mw 25 e 05; i2c mw 25 16 f2\0" \
+                                       "displayimg=unzip 200d0000 67000000; mw.l 138000b4 0059f9ff; mw.l 138001a0 67e10000; mw.l 13800200 00001680; mw.l 13801410 1; mw.l 13802040 e0000018; sleep 1; mw.l 13802040 e0000008\0" \
+                                       "download=echo Thor mode enabled; run muicsetusb; run displayimg; mw.l 0x105c080c 0; thor 0 mmc 0\0"
 #define CONFIG_MENUPROMPT              "Loading, please wait..."
 
 #define CONFIG_ENV_SIZE                        0x1000