(vf->height > (default_height + 8)))
return true;
+ /*true bypass for 720p above*/
+ if ((vf->flag & VFRAME_FLAG_GAME_MODE) &&
+ (vf->width > 720))
+ return true;
+
return false;
}
MODULE_PARM_DESC(tx_op_color_primary,
"tx output color_primary");
+unsigned int debug_game_mode_1;
+module_param(debug_game_mode_1, uint, 0664);
+MODULE_PARM_DESC(debug_game_mode_1, "\n debug_game_mode_1\n");
unsigned int pq_user_value;
unsigned int hdr_source_type = 0x1;
WRITE_VPP_REG(VI_HIST_GCLK_CTRL, 0xffffffff);
WRITE_VPP_REG_BITS(VI_HIST_CTRL, 2, VI_HIST_POW_BIT, VI_HIST_POW_WID);
}
-
+static unsigned int vpp_luma_max;
void vpp_get_vframe_hist_info(struct vframe_s *vf)
{
unsigned int hist_height, hist_width;
VI_HIST_ON_BIN_62_BIT, VI_HIST_ON_BIN_62_WID);
vf->prop.hist.vpp_gamma[63] = READ_VPP_REG_BITS(VI_DNLP_HIST31,
VI_HIST_ON_BIN_63_BIT, VI_HIST_ON_BIN_63_WID);
+ if (debug_game_mode_1 &&
+ (vpp_luma_max != vf->prop.hist.vpp_luma_max)) {
+ vf->ready_clock_hist[1] = sched_clock();
+ pr_info("vpp output done %lld us. luma_max(0x%x-->0x%x)\n",
+ vf->ready_clock_hist[1]/1000,
+ vpp_luma_max, vf->prop.hist.vpp_luma_max);
+ vpp_luma_max = vf->prop.hist.vpp_luma_max;
+ }
}
static void ioctrl_get_hdr_metadata(struct vframe_s *vf)
#else
video_vf_put(cur_dispbuf);
#endif
+ if (debug_flag & DEBUG_FLAG_LATENCY) {
+ vf->ready_clock[3] = sched_clock();
+ pr_info("video toggle latency %lld ms video get latency %lld ms vdin put latency %lld ms. first %lld ms.\n",
+ vf->ready_clock[3]/1000,
+ vf->ready_clock[2]/1000,
+ vf->ready_clock[1]/1000,
+ vf->ready_clock[0]/1000);
+ cur_dispbuf->ready_clock[4] = sched_clock();
+ pr_info("video put latency %lld ms video toggle latency %lld ms video get latency %lld ms vdin put latency %lld ms. first %lld ms.\n",
+ cur_dispbuf->ready_clock[4]/1000,
+ cur_dispbuf->ready_clock[3]/1000,
+ cur_dispbuf->ready_clock[2]/1000,
+ cur_dispbuf->ready_clock[1]/1000,
+ cur_dispbuf->ready_clock[0]/1000);
+ }
}
} else
if ((freerun_mode == FREERUN_NODUR) || hdmi_in_onvideo)
return true;
+ /*freerun for game mode*/
+ if (next_vf->flag & VFRAME_FLAG_GAME_MODE)
+ return true;
if (step_enable) {
if (step_flag)
vf = video_vf_get();
if (!vf)
break;
+ if (debug_flag & DEBUG_FLAG_LATENCY) {
+ vf->ready_clock[2] = sched_clock();
+ pr_info("video get latency %lld ms vdin put latency %lld ms. first %lld ms.\n",
+ vf->ready_clock[2]/1000,
+ vf->ready_clock[1]/1000,
+ vf->ready_clock[0]/1000);
+ }
if (video_vf_dirty_put(vf))
break;
if (vf && hdmiin_frame_check && (vf->source_type ==
#define DEBUG_FLAG_RDMA_WAIT_1 0x40000
#define DEBUG_FLAG_VSYNC_DONONE 0x80000
#define DEBUG_FLAG_GOFIELD_MANUL 0x100000
-
+#define DEBUG_FLAG_LATENCY 0x200000
/*for video.c's static int debug_flag;*/
#define VOUT_TYPE_TOP_FIELD 0
/*backup before roundup*/
devp->canvas_active_w = devp->canvas_w;
if (devp->force_yuv444_malloc == 1) {
- if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH)
+ if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
+ (devp->color_depth_mode != 1))
devp->canvas_w = devp->h_active *
VDIN_YUV444_10BIT_PER_PIXEL_BYTE;
else
/*backup before roundup*/
devp->canvas_active_w = devp->canvas_w;
if (devp->force_yuv444_malloc == 1) {
- if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH)
+ if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
+ (devp->color_depth_mode != 1))
devp->canvas_w = devp->h_active *
VDIN_YUV444_10BIT_PER_PIXEL_BYTE;
else
}
#ifdef CONFIG_CMA
+/* need to be static for pointer use in codec_mm */
+static char vdin_name[6];
/* return val:1: fail;0: ok */
unsigned int vdin_cma_alloc(struct vdin_dev_s *devp)
{
- char vdin_name[6];
unsigned int mem_size, h_size, v_size;
int flags = CODEC_MM_FLAGS_CMA_FIRST|CODEC_MM_FLAGS_CMA_CLEAR|
CODEC_MM_FLAGS_CPU;
unsigned int max_buffer_num = min_buf_num;
unsigned int i;
- if (devp->rdma_enable && (devp->game_mode == 0))
+ if (devp->rdma_enable)
max_buffer_num++;
/*todo: need update if vf_skip_cnt used by other port*/
if (devp->vfp->skip_vf_num &&
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_GBR) ||
(devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG) ||
(devp->force_yuv444_malloc == 1)) {
- if (devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) {
+ if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) &&
+ (devp->color_depth_mode != 1)) {
h_size = roundup(h_size *
VDIN_YUV444_10BIT_PER_PIXEL_BYTE,
devp->canvas_align);
module_param(vdin_ctl_dbg, int, 0664);
MODULE_PARM_DESC(vdin_ctl_dbg, "vdin_ctl_dbg");
+/*bit0/1:game mode enable for vdin0/1*/
+unsigned int game_mode;
+module_param(game_mode, uint, 0664);
+MODULE_PARM_DESC(game_mode, "game_mode");
static unsigned int vpu_reg_27af = 0x3;
/***************************Local defines**********************************/
/* win_ve */
wr_bits(offset, VDIN_WR_V_START_END, (v - 1), WR_VEND_BIT, WR_VEND_WID);
/* hconv_mode */
- wr_bits(offset, VDIN_WR_CTRL, 0, HCONV_MODE_BIT, HCONV_MODE_WID);
+ wr_bits(offset, VDIN_WR_CTRL, 2, HCONV_MODE_BIT, HCONV_MODE_WID);
/* vconv_mode */
wr_bits(offset, VDIN_WR_CTRL, 0, VCONV_MODE_BIT, VCONV_MODE_WID);
if (write_format444 == 2) {
} else if (write_format444 == 1) {
vconv_mode = 3;
} else {
+ hconv_mode = 2;
swap_cbcr = 0;
}
#ifdef CONFIG_AML_RDMA
wr_bits(offset, VDIN_HIST_CTRL, 1, 8, 1);
}
#endif
-
+static unsigned int vdin_luma_max;
void vdin_set_vframe_prop_info(struct vframe_s *vf,
struct vdin_dev_s *devp)
{
/* fetch meas info - For M2 or further chips only, not for M1 chip */
vf->prop.meas.vs_stamp = devp->stamp;
vf->prop.meas.vs_cycle = devp->cycle;
+ if ((vdin_ctl_dbg & (1 << 8)) &&
+ (vdin_luma_max != vf->prop.hist.luma_max)) {
+ vf->ready_clock_hist[0] = sched_clock();
+ pr_info("vdin write done %lld us. lum_max(0x%x-->0x%x)\n",
+ vf->ready_clock_hist[0]/1000,
+ vdin_luma_max, vf->prop.hist.luma_max);
+ vdin_luma_max = vf->prop.hist.luma_max;
+ }
#if 0
/*#ifdef CONFIG_AML_LOCAL_DIMMING*/
/* get ldim max */
}
index_disp = req->vf->index_disp & 0xff;
if (index_disp >= VFRAME_DISP_MAX_NUM) {
- if (vdin_ctl_dbg)
+ if (vdin_ctl_dbg&(1<<2))
pr_info("%s:req->vf->index_disp(%d) is overflow!\n",
__func__, index_disp);
return -1;
}
- req->disp_mode = p->disp_mode[index_disp];
+ if (game_mode)
+ req->disp_mode = VFRAME_DISP_MODE_NULL;
+ else
+ req->disp_mode = p->disp_mode[index_disp];
if ((req->req_mode == 1) && (p->skip_vf_num))
p->disp_mode[index_disp] = VFRAME_DISP_MODE_UNKNOWN;
- if (vdin_ctl_dbg)
+ if (vdin_ctl_dbg&(1<<1))
pr_info("%s(type 0x%x vf index 0x%x)=>disp_mode %d,req_mode:%d\n",
__func__, type, index_disp, req->disp_mode,
req->req_mode);
};
#endif
+extern unsigned int game_mode;
/* ************************************************************************ */
/* ******** GLOBAL FUNCTION CLAIM ******** */
vdin_dump_vf_state(devp->vfp);
if (vf) {
pr_info("current vframe index(%u):\n", vf->index);
- pr_info("\t buf(w%u, h%u),type(0x%x, %u), duration(%d),",
- vf->width, vf->height, vf->type, vf->type, vf->duration);
+ pr_info("\t buf(w%u, h%u),type(0x%x),flag(0x%x), duration(%d),",
+ vf->width, vf->height, vf->type, vf->flag, vf->duration);
pr_info("\t ratio_control(0x%x).\n", vf->ratio_control);
pr_info("\t trans fmt %u, left_start_x %u,",
vf->trans_fmt, vf->left_eye.start_x);
curparm->reserved, devp->flags);
pr_info("max buffer num %u, msr_clk_val:%d.\n",
devp->canvas_max_num, devp->msr_clk_val);
- pr_info("canvas buffer size %u, rdma_enable: %d, game_mode: %d.\n",
- devp->canvas_max_size, devp->rdma_enable, devp->game_mode);
+ pr_info("canvas buffer size %u, rdma_enable: %d.\n",
+ devp->canvas_max_size, devp->rdma_enable);
pr_info("range(%d),csc_cfg:0x%x,urgent_en:%d\n",
devp->prop.color_fmt_range,
devp->csc_cfg, devp->urgent_en);
module_param(vdin_drop_cnt, uint, 0664);
MODULE_PARM_DESC(vdin_drop_cnt, "vdin_drop_cnt");
-static bool game_mode;
-module_param(game_mode, bool, 0664);
-MODULE_PARM_DESC(game_mode, "game_mode");
static int irq_max_count;
pr_info("%s ok\n", __func__);
}
-
+static void vdin_game_mode_check(struct vdin_dev_s *devp)
+{
+ if ((game_mode == 1) &&
+ (devp->parm.port != TVIN_PORT_CVBS3)) {
+ if (devp->h_active > 720 && ((devp->parm.info.fps == 50) ||
+ (devp->parm.info.fps == 60)))
+ devp->game_mode = 3;
+ else
+ devp->game_mode = 1;
+ } else
+ devp->game_mode = 0;
+}
/*
*based on the bellow parameters:
* a.h_active (vf->width = devp->h_active)
vf->index = i;
vf->width = devp->h_active;
vf->height = devp->v_active;
+ if (devp->game_mode != 0)
+ vf->flag |= VFRAME_FLAG_GAME_MODE;
scan_mode = devp->fmt_info_p->scan_mode;
if (((scan_mode == TVIN_SCAN_MODE_INTERLACED) &&
(!(devp->parm.flag & TVIN_PARM_FLAG_2D_TO_3D) &&
vdin_get_format_convert(devp);
devp->curr_wr_vfe = NULL;
- devp->game_mode = game_mode;
- if (game_mode)
- devp->vfp->skip_vf_num = 1;
- else
- devp->vfp->skip_vf_num = devp->prop.skip_vf_num;
+ devp->vfp->skip_vf_num = devp->prop.skip_vf_num;
if (devp->vfp->skip_vf_num >= VDIN_CANVAS_MAX_CNT)
devp->vfp->skip_vf_num = 0;
devp->canvas_config_mode = canvas_config_mode;
devp->vfp->size = devp->canvas_max_num;
vf_pool_init(devp->vfp, devp->vfp->size);
+ vdin_game_mode_check(devp);
vdin_vf_init(devp);
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
if ((devp->dv.dolby_input & (1 << devp->index)) ||
if (!devp->curr_wr_vfe) {
devp->curr_wr_vfe = provider_vf_get(devp->vfp);
devp->curr_wr_vfe->vf.ready_jiffies64 = jiffies_64;
+ devp->curr_wr_vfe->vf.ready_clock[0] = sched_clock();
/*save the first field stamp*/
devp->stamp = stamp;
devp->vdin_irq_flag = 3;
- vdin_drop_cnt++;
goto irq_handled;
}
if (devp->last_wr_vfe && (devp->flags&VDIN_FLAG_RDMA_ENABLE) &&
- (devp->game_mode == false)) {
+ !(devp->game_mode & (1 << 1))) {
/*dolby vision metadata process*/
if (dv_dbg_mask & DV_UPDATE_DATA_MODE_DELBY_WORK
&& devp->dv.dv_config) {
} else
devp->dv.dv_crc_check = true;
if ((devp->dv.dv_crc_check == true) ||
- (!(dv_dbg_mask & DV_CRC_CHECK)))
+ (!(dv_dbg_mask & DV_CRC_CHECK))) {
provider_vf_put(devp->last_wr_vfe, devp->vfp);
- else {
+ if (time_en) {
+ devp->last_wr_vfe->vf.ready_clock[1] =
+ sched_clock();
+ pr_info("vdin put latency %lld us. first %lld us.\n",
+ devp->last_wr_vfe->vf.ready_clock[1]/1000,
+ devp->last_wr_vfe->vf.ready_clock[0]/1000);
+ }
+ } else {
devp->vdin_irq_flag = 15;
vdin_drop_cnt++;
goto irq_handled;
if (!next_wr_vfe) {
devp->vdin_irq_flag = 14;
vdin_drop_cnt++;
+ vf_drop_cnt = vdin_drop_cnt;/*avoid do skip*/
goto irq_handled;
}
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
/*if vdin-nr,di must get
* vdin current field type which di pre will read
*/
- if (vdin2nr || (devp->flags & VDIN_FLAG_RDMA_ENABLE))
+ if ((vdin2nr || (devp->flags & VDIN_FLAG_RDMA_ENABLE)) &&
+ !(devp->game_mode & (1 << 1)))
curr_wr_vf->type = devp->curr_field_type;
else
curr_wr_vf->type = last_field_type;
if (devp->auto_ratio_en && (devp->parm.port >= TVIN_PORT_CVBS0) &&
(devp->parm.port <= TVIN_PORT_CVBS3))
vdin_set_display_ratio(devp, curr_wr_vf);
- if (devp->flags&VDIN_FLAG_RDMA_ENABLE && (devp->game_mode == false)) {
+ if ((devp->flags&VDIN_FLAG_RDMA_ENABLE) &&
+ !(devp->game_mode & (1 << 1))) {
devp->last_wr_vfe = curr_wr_vfe;
} else {
/*dolby vision metadata process*/
} else
devp->dv.dv_crc_check = true;
if ((devp->dv.dv_crc_check == true) ||
- (!(dv_dbg_mask & DV_CRC_CHECK)))
+ (!(dv_dbg_mask & DV_CRC_CHECK))) {
provider_vf_put(curr_wr_vfe, devp->vfp);
- else {
+ if (vdin_dbg_en) {
+ curr_wr_vfe->vf.ready_clock[1] = sched_clock();
+ pr_info("vdin put latency %lld us. first %lld us.\n",
+ curr_wr_vfe->vf.ready_clock[1]/1000,
+ curr_wr_vfe->vf.ready_clock[0]/1000);
+ }
+ } else {
devp->vdin_irq_flag = 15;
vdin_drop_cnt++;
goto irq_handled;
devp->curr_wr_vfe = next_wr_vfe;
/* debug for video latency */
next_wr_vfe->vf.ready_jiffies64 = jiffies_64;
+ next_wr_vfe->vf.ready_clock[0] = sched_clock();
- if (!(devp->flags&VDIN_FLAG_RDMA_ENABLE) || (devp->game_mode == true)) {
+ if (!(devp->flags&VDIN_FLAG_RDMA_ENABLE) ||
+ (devp->game_mode & (1 << 1))) {
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
if (((devp->dv.dolby_input & (1 << devp->index)) ||
(devp->dv.dv_flag && is_dolby_vision_enable())) &&
if (vdin_dbg_en)
pr_info("TVIN_IOC_SNOWOFF(%d) ok\n\n", devp->index);
break;
+ case TVIN_IOC_GAME_MODE:
+ if (copy_from_user(&game_mode, argp, sizeof(unsigned int))) {
+ ret = -EFAULT;
+ break;
+ }
+ if (vdin_dbg_en)
+ pr_info("TVIN_IOC_GAME_MODE(%d) done\n\n", game_mode);
+ break;
case TVIN_IOC_GET_COLOR_RANGE:
if (copy_to_user(argp,
&color_range_force,
vdevp->rdma_enable = 1;
/*set vdin_dev_s size*/
vdevp->vdin_dev_ssize = sizeof(struct vdin_dev_s);
- vdevp->game_mode = game_mode;
vdevp->canvas_config_mode = canvas_config_mode;
INIT_DELAYED_WORK(&vdevp->dv.dv_dwork, vdin_dv_dwork);
#include "vdin_vf.h"
#include "vdin_regs.h"
-#define VDIN_VER "Ref.2017/011/17"
+#define VDIN_VER "Ref.2018/04/28"
/*the counter of vdin*/
#define VDIN_MAX_DEVS 2
unsigned int color_range_mode;
/*auto detect av/atv input ratio*/
unsigned int auto_ratio_en;
- bool game_mode;/*1:game mode for hdmi*/
+ /*
+ *game_mode:
+ *bit0:enable/disable
+ *bit1:for true bypas and put vframe in advance one vsync
+ */
+ unsigned int game_mode;
unsigned int rdma_enable;
unsigned int canvas_config_mode;
bool prehsc_en;
static int sm_atv_prestable_fmt;
static int sm_print_prestable;
-static bool sm_debug_enable = true;
-module_param(sm_debug_enable, bool, 0664);
+/*bit0:general debug bit;bit1:hdmirx color change*/
+static unsigned int sm_debug_enable = 1;
+module_param(sm_debug_enable, uint, 0664);
MODULE_PARM_DESC(sm_debug_enable,
"enable/disable state machine debug message");
(vdin_hdr_flag != pre_vdin_hdr_flag) ||
(vdin_fmt_range != pre_vdin_fmt_range) ||
(cur_dest_color_fmt != pre_dest_color_fmt)) {
- pr_info("[smr.%d] cur color fmt(%d->%d), hdr_flag(%d->%d), dest color fmt(%d->%d), csc_cfg:0x%x\n",
- devp->index,
- pre_color_fmt, cur_color_fmt,
- pre_vdin_hdr_flag, vdin_hdr_flag,
- pre_dest_color_fmt, cur_dest_color_fmt,
- devp->csc_cfg);
+ if (sm_debug_enable & (1 << 1))
+ pr_info("[smr.%d] cur color fmt(%d->%d), hdr_flag(%d->%d), dest color fmt(%d->%d), csc_cfg:0x%x\n",
+ devp->index,
+ pre_color_fmt, cur_color_fmt,
+ pre_vdin_hdr_flag, vdin_hdr_flag,
+ pre_dest_color_fmt, cur_dest_color_fmt,
+ devp->csc_cfg);
vdin_get_format_convert(devp);
devp->csc_cfg = 1;
} else
}
EXPORT_SYMBOL(tvin_get_sm_status);
+int tvin_get_av_status(void)
+{
+ if (tvin_get_sm_status(0) == TVIN_SM_STATUS_STABLE)
+ return true;
+
+ return false;
+}
+EXPORT_SYMBOL(tvin_get_av_status);
+
#define VF_FLAG_NORMAL_FRAME 0x00000001
#define VF_FLAG_FREEZED_FRAME 0x00000002
-#define VFRAME_DISP_MAX_NUM 10
+#define VFRAME_DISP_MAX_NUM 20
#define VDIN_VF_POOL_FREEZE 0x00000001
#define ISR_LOG_EN
enum tvin_force_color_range_e)
#define TVIN_IOC_SET_COLOR_RANGE _IOW(_TM_T, 0X4a,\
enum tvin_force_color_range_e)
-
+#define TVIN_IOC_GAME_MODE _IOW(_TM_T, 0x4b, unsigned int)
/* TVAFE */
#define TVIN_IOC_S_AFE_VGA_PARM _IOW(_TM_T, 0x16, struct tvafe_vga_parm_s)
#define TVIN_IOC_G_AFE_VGA_PARM _IOR(_TM_T, 0x17, struct tvafe_vga_parm_s)
#define VFRAME_FLAG_HIGH_BANDWIDTH 4
#define VFRAME_FLAG_ERROR_RECOVERY 8
#define VFRAME_FLAG_SYNCFRAME 0x10
+#define VFRAME_FLAG_GAME_MODE 0x20
enum pixel_aspect_ratio_e {
PIXEL_ASPECT_RATIO_1_1,
/* pixel aspect ratio */
enum pixel_aspect_ratio_e pixel_ratio;
u64 ready_jiffies64; /* ready from decode on jiffies_64 */
+ long long ready_clock[5];/*ns*/
+ long long ready_clock_hist[2];/*ns*/
atomic_t use_cnt;
u32 frame_dirty;
/*
struct provider_disp_mode_req_s {
/*input*/
struct vframe_s *vf;
- unsigned int req_mode;/*0:peak;1:get*/
+ unsigned int req_mode;/*0:get;1:check*/
/*output*/
enum vframe_disp_mode_e disp_mode;
};