HDLCD: Limit the pixel clock to 165MHz to match TDA19988 specs.

The DT set the upper limit for the pixel clock to 210MHz. While
technically the TDA19988 chip works at that frequency, it is
outside the spec sheet values. Restrict the clock range to the
published values.

Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>

diff --git a/arch/arm64/boot/dts/juno.dts b/arch/arm64/boot/dts/juno.dts
index 001edb792b4cf1d07c90654f6bc989a20ad43ced..be5bf734846723d533931b48ba50d3b394d66665 100644 (file)
--- a/arch/arm64/boot/dts/juno.dts
+++ b/arch/arm64/boot/dts/juno.dts
@@ -255,7 +255,7 @@
                        compatible = "arm,scpi-clk-range";
                        #clock-cells = <1>;
                        clock-indices = <3>, <4>;
-                       frequency-range = <23000000 210000000>;
+                       frequency-range = <23750000 165000000>;
                        clock-output-names = "pxlclk0", "pxlclk1";
                };