arm: socfpga: Convert clock manager from struct to defines
authorLey Foon Tan <ley.foon.tan@intel.com>
Fri, 8 Nov 2019 02:38:21 +0000 (10:38 +0800)
committerMarek Vasut <marex@denx.de>
Tue, 7 Jan 2020 13:38:33 +0000 (14:38 +0100)
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get clock manager base address from DT node instead of using
#define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
arch/arm/mach-socfpga/clock_manager.c
arch/arm/mach-socfpga/clock_manager_arria10.c
arch/arm/mach-socfpga/clock_manager_gen5.c
arch/arm/mach-socfpga/clock_manager_s10.c
arch/arm/mach-socfpga/include/mach/clock_manager.h
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
arch/arm/mach-socfpga/misc.c
drivers/mmc/socfpga_dw_mmc.c

index 9f3c643..dbb10ec 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 void cm_wait_for_lock(u32 mask)
 {
        u32 inter_val;
        u32 retry = 0;
        do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-               inter_val = readl(&clock_manager_base->inter) & mask;
+               inter_val = readl(socfpga_get_clkmgr_addr() +
+                                 CLKMGR_INTER) & mask;
 #else
-               inter_val = readl(&clock_manager_base->stat) & mask;
+               inter_val = readl(socfpga_get_clkmgr_addr() +
+                                 CLKMGR_STAT) & mask;
 #endif
                /* Wait for stable lock */
                if (inter_val == mask)
@@ -36,8 +35,9 @@ void cm_wait_for_lock(u32 mask)
 /* function to poll in the fsm busy bit */
 int cm_wait_for_fsm(void)
 {
-       return wait_for_bit_le32(&clock_manager_base->stat,
-                                CLKMGR_STAT_BUSY, false, 20000, false);
+       return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
+                                CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
+                                false);
 }
 
 int set_cpu_clk_info(void)
index 334a79f..392f2eb 100644 (file)
@@ -231,9 +231,6 @@ static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
        return 0;
 }
 
-static const struct socfpga_clock_manager *clock_manager_base =
-       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 /* calculate the intended main VCO frequency based on handoff */
 static unsigned int cm_calc_handoff_main_vco_clk_hz
                                        (struct mainpll_cfg *main_cfg)
@@ -551,12 +548,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
                writel((main_cfg->vco1_denom <<
                        CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
                        cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
-                       &clock_manager_base->main_pll.vco1);
+                       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
                mdelay(1);
                cm_wait_for_lock(LOCKED_MASK);
        }
        writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
-               main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);
+               main_cfg->vco1_numer,
+               socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
        mdelay(1);
        cm_wait_for_lock(LOCKED_MASK);
 }
@@ -579,14 +577,18 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
        /* execute the ramping here */
        for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
             clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
-               writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
-                       cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
-                       &clock_manager_base->per_pll.vco1);
+               writel((per_cfg->vco1_denom <<
+                             CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+                             cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
+                                                    clk_hz),
+                             socfpga_get_clkmgr_addr() +
+                             CLKMGR_A10_PERPLL_VCO1);
                mdelay(1);
                cm_wait_for_lock(LOCKED_MASK);
        }
        writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
-               per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);
+                     per_cfg->vco1_numer,
+                     socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
        mdelay(1);
        cm_wait_for_lock(LOCKED_MASK);
 }
@@ -638,16 +640,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
        /* gate off all mainpll clock excpet HW managed clock */
        writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
                CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
-               &clock_manager_base->main_pll.enr);
+               socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENR);
 
        /* now we can gate off the rest of the peripheral clocks */
-       writel(0, &clock_manager_base->per_pll.en);
+       writel(0, socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EN);
 
        /* Put all plls in external bypass */
        writel(CLKMGR_MAINPLL_BYPASS_RESET,
-              &clock_manager_base->main_pll.bypasss);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSS);
        writel(CLKMGR_PERPLL_BYPASS_RESET,
-              &clock_manager_base->per_pll.bypasss);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSS);
 
        /*
         * Put all plls VCO registers back to reset value.
@@ -657,15 +659,17 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
        writel(CLKMGR_MAINPLL_VCO0_RESET |
               CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
               (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
-              &clock_manager_base->main_pll.vco0);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0);
 
        writel(CLKMGR_PERPLL_VCO0_RESET |
               CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
               (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
-              &clock_manager_base->per_pll.vco0);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0);
 
-       writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1);
-       writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1);
+       writel(CLKMGR_MAINPLL_VCO1_RESET,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
+       writel(CLKMGR_PERPLL_VCO1_RESET,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 
        /* clear the interrupt register status register */
        writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
@@ -676,7 +680,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
                CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
                CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
                CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
-               &clock_manager_base->intr);
+               socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR);
 
        /* Program VCO Numerator and Denominator for main PLL */
        ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
@@ -687,14 +691,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
                else if (ramp_required == 2)
                        pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 
-               writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+               writel((main_cfg->vco1_denom <<
+                       CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
                        cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
                                               pll_ramp_main_hz),
-                       &clock_manager_base->main_pll.vco1);
+                       socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
        } else
-               writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
-                       main_cfg->vco1_numer,
-                       &clock_manager_base->main_pll.vco1);
+               writel((main_cfg->vco1_denom <<
+                      CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+                      main_cfg->vco1_numer,
+                      socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
 
        /* Program VCO Numerator and Denominator for periph PLL */
        ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
@@ -707,23 +713,25 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
                        pll_ramp_periph_hz =
                                CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 
-               writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+               writel((per_cfg->vco1_denom <<
+                       CLKMGR_PERPLL_VCO1_DENOM_LSB) |
                        cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
                                               pll_ramp_periph_hz),
-                       &clock_manager_base->per_pll.vco1);
+                       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
        } else
-               writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+               writel((per_cfg->vco1_denom <<
+                       CLKMGR_PERPLL_VCO1_DENOM_LSB) |
                        per_cfg->vco1_numer,
-                       &clock_manager_base->per_pll.vco1);
+                       socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 
        /* Wait for at least 5 us */
        udelay(5);
 
        /* Now deassert BGPWRDN and PWRDN */
-       clrbits_le32(&clock_manager_base->main_pll.vco0,
+       clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
                     CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
                     CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
-       clrbits_le32(&clock_manager_base->per_pll.vco0,
+       clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
                     CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
                     CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
 
@@ -731,84 +739,92 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
        udelay(7);
 
        /* enable the VCO and disable the external regulator to PLL */
-       writel((readl(&clock_manager_base->main_pll.vco0) &
+       writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
                ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
                CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
-               &clock_manager_base->main_pll.vco0);
-       writel((readl(&clock_manager_base->per_pll.vco0) &
+               socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0);
+       writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0) &
                ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
                CLKMGR_PERPLL_VCO0_EN_SET_MSK,
-               &clock_manager_base->per_pll.vco0);
+               socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0);
 
        /* setup all the main PLL counter and clock source */
        writel(main_cfg->nocclk,
-              SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_NOCCLK);
        writel(main_cfg->mpuclk,
-              SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_MPUCLK);
 
        /* main_emaca_clk divider */
-       writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk);
+       writel(main_cfg->cntr2clk_cnt,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR2CLK);
        /* main_emacb_clk divider */
-       writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk);
+       writel(main_cfg->cntr3clk_cnt,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR3CLK);
        /* main_emac_ptp_clk divider */
-       writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk);
+       writel(main_cfg->cntr4clk_cnt,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR4CLK);
        /* main_gpio_db_clk divider */
-       writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk);
+       writel(main_cfg->cntr5clk_cnt,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR5CLK);
        /* main_sdmmc_clk divider */
-       writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk);
+       writel(main_cfg->cntr6clk_cnt,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR6CLK);
        /* main_s2f_user0_clk divider */
        writel(main_cfg->cntr7clk_cnt |
               (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
-              &clock_manager_base->main_pll.cntr7clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR7CLK);
        /* main_s2f_user1_clk divider */
-       writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk);
+       writel(main_cfg->cntr8clk_cnt,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR8CLK);
        /* main_hmc_pll_clk divider */
        writel(main_cfg->cntr9clk_cnt |
               (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
-              &clock_manager_base->main_pll.cntr9clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR9CLK);
        /* main_periph_ref_clk divider */
        writel(main_cfg->cntr15clk_cnt,
-              &clock_manager_base->main_pll.cntr15clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR15CLK);
 
        /* setup all the peripheral PLL counter and clock source */
        /* peri_emaca_clk divider */
        writel(per_cfg->cntr2clk_cnt |
               (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
-              &clock_manager_base->per_pll.cntr2clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR2CLK);
        /* peri_emacb_clk divider */
        writel(per_cfg->cntr3clk_cnt |
               (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
-              &clock_manager_base->per_pll.cntr3clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR3CLK);
        /* peri_emac_ptp_clk divider */
        writel(per_cfg->cntr4clk_cnt |
               (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
-              &clock_manager_base->per_pll.cntr4clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR4CLK);
        /* peri_gpio_db_clk divider */
        writel(per_cfg->cntr5clk_cnt |
               (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
-              &clock_manager_base->per_pll.cntr5clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR5CLK);
        /* peri_sdmmc_clk divider */
        writel(per_cfg->cntr6clk_cnt |
               (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
-              &clock_manager_base->per_pll.cntr6clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR6CLK);
        /* peri_s2f_user0_clk divider */
-       writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);
+       writel(per_cfg->cntr7clk_cnt,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR7CLK);
        /* peri_s2f_user1_clk divider */
        writel(per_cfg->cntr8clk_cnt |
               (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
-              &clock_manager_base->per_pll.cntr8clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR8CLK);
        /* peri_hmc_pll_clk divider */
-       writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);
+       writel(per_cfg->cntr9clk_cnt,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR9CLK);
 
        /* setup all the external PLL counter */
        /* mpu wrapper / external divider */
        writel(main_cfg->mpuclk_cnt |
               (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
-              &clock_manager_base->main_pll.mpuclk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_MPUCLK);
        /* NOC wrapper / external divider */
        writel(main_cfg->nocclk_cnt |
               (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
-              &clock_manager_base->main_pll.nocclk);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCCLK);
        /* NOC subclock divider such as l4 */
        writel(main_cfg->nocdiv_l4mainclk |
               (main_cfg->nocdiv_l4mpclk <<
@@ -821,10 +837,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
                CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
               (main_cfg->nocdiv_cspdbclk <<
                CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
-               &clock_manager_base->main_pll.nocdiv);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCDIV);
        /* gpio_db external divider */
        writel(per_cfg->gpiodiv_gpiodbclk,
-              &clock_manager_base->per_pll.gpiodiv);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_GPIOFIV);
 
        /* setup the EMAC clock mux select */
        writel((per_cfg->emacctl_emac0sel <<
@@ -833,7 +849,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
                CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
               (per_cfg->emacctl_emac2sel <<
                CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
-              &clock_manager_base->per_pll.emacctl);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EMACCTL);
 
        /* at this stage, check for PLL lock status */
        cm_wait_for_lock(LOCKED_MASK);
@@ -843,33 +859,33 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
         * assert/deassert outresetall
         */
        /* assert mainpll outresetall */
-       setbits_le32(&clock_manager_base->main_pll.vco0,
+       setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
                     CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
        /* assert perpll outresetall */
-       setbits_le32(&clock_manager_base->per_pll.vco0,
+       setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
                     CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
        /* de-assert mainpll outresetall */
-       clrbits_le32(&clock_manager_base->main_pll.vco0,
+       clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
                     CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
        /* de-assert perpll outresetall */
-       clrbits_le32(&clock_manager_base->per_pll.vco0,
+       clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0,
                     CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 
        /* Take all PLLs out of bypass when boot mode is cleared. */
        /* release mainpll from bypass */
        writel(CLKMGR_MAINPLL_BYPASS_RESET,
-              &clock_manager_base->main_pll.bypassr);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR);
        /* wait till Clock Manager is not busy */
        cm_wait_for_fsm();
 
        /* release perpll from bypass */
        writel(CLKMGR_PERPLL_BYPASS_RESET,
-              &clock_manager_base->per_pll.bypassr);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR);
        /* wait till Clock Manager is not busy */
        cm_wait_for_fsm();
 
        /* clear boot mode */
-       clrbits_le32(&clock_manager_base->ctrl,
+       clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
                     CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
        /* wait till Clock Manager is not busy */
        cm_wait_for_fsm();
@@ -882,9 +898,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 
        /* Now ungate non-hw-managed clocks */
        writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
-               CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
-               &clock_manager_base->main_pll.ens);
-       writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens);
+              CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENS);
+       writel(CLKMGR_PERPLL_EN_RESET,
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_ENS);
 
        /* Clear the loss lock and slip bits as they might set during
        clock reconfiguration */
@@ -894,14 +911,14 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
               CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
               CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
               CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
-              &clock_manager_base->intr);
+              socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR);
 
        return 0;
 }
 
 static void cm_use_intosc(void)
 {
-       setbits_le32(&clock_manager_base->ctrl,
+       setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
                     CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
 }
 
index 54a821a..8fa2760 100644 (file)
 #include <asm/arch/clock_manager.h>
 #include <wait_bit.h>
 
-static const struct socfpga_clock_manager *clock_manager_base =
-       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 /*
  * function to write the bypass register which requires a poll of the
  * busy bit
  */
 static void cm_write_bypass(u32 val)
 {
-       writel(val, &clock_manager_base->bypass);
+       writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_BYPASS);
        cm_wait_for_fsm();
 }
 
 /* function to write the ctrl register which requires a poll of the busy bit */
 static void cm_write_ctrl(u32 val)
 {
-       writel(val, &clock_manager_base->ctrl);
+       writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL);
        cm_wait_for_fsm();
 }
 
@@ -80,8 +77,8 @@ int cm_basic_init(const struct cm_config * const cfg)
         * gatting off the rest of the periperal clocks.
         */
        writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
-               readl(&clock_manager_base->per_pll.en),
-               &clock_manager_base->per_pll.en);
+               readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN),
+               socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
 
        /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
        writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
@@ -90,12 +87,12 @@ int cm_basic_init(const struct cm_config * const cfg)
                CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
                CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
                CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
-               &clock_manager_base->main_pll.en);
+               socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN);
 
-       writel(0, &clock_manager_base->sdr_pll.en);
+       writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN);
 
        /* now we can gate off the rest of the peripheral clocks */
-       writel(0, &clock_manager_base->per_pll.en);
+       writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
 
        /* Put all plls in bypass */
        cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
@@ -104,13 +101,13 @@ int cm_basic_init(const struct cm_config * const cfg)
        /* Put all plls VCO registers back to reset value. */
        writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
               ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
-              &clock_manager_base->main_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
        writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
               ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
-              &clock_manager_base->per_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
        writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
               ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
-              &clock_manager_base->sdr_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
        /*
         * The clocks to the flash devices and the L4_MAIN clocks can
@@ -120,23 +117,26 @@ int cm_basic_init(const struct cm_config * const cfg)
         * after exiting safe mode but before ungating the clocks.
         */
        writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
-              &clock_manager_base->per_pll.src);
+                     socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
        writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
-              &clock_manager_base->main_pll.l4src);
+                     socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
 
        /* read back for the required 5 us delay. */
-       readl(&clock_manager_base->main_pll.vco);
-       readl(&clock_manager_base->per_pll.vco);
-       readl(&clock_manager_base->sdr_pll.vco);
+       readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+       readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+       readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
 
        /*
         * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
         * with numerator and denominator.
         */
-       writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
-       writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
-       writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
+       writel(cfg->main_vco_base,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
+       writel(cfg->peri_vco_base,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
+       writel(cfg->sdram_vco_base,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
        /*
         * Time starts here. Must wait 7 us from
@@ -145,44 +145,55 @@ int cm_basic_init(const struct cm_config * const cfg)
        end = timer_get_us() + 7;
 
        /* main mpu */
-       writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
+       writel(cfg->mpuclk,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK);
 
        /* altera group mpuclk */
-       writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
+       writel(cfg->altera_grp_mpuclk,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK);
 
        /* main main clock */
-       writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
+       writel(cfg->mainclk,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINCLK);
 
        /* main for dbg */
-       writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
+       writel(cfg->dbgatclk,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGATCLK);
 
        /* main for cfgs2fuser0clk */
        writel(cfg->cfg2fuser0clk,
-              &clock_manager_base->main_pll.cfgs2fuser0clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK);
 
        /* Peri emac0 50 MHz default to RMII */
-       writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
+       writel(cfg->emac0clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC0CLK);
 
        /* Peri emac1 50 MHz default to RMII */
-       writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
+       writel(cfg->emac1clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC1CLK);
 
        /* Peri QSPI */
-       writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
+       writel(cfg->mainqspiclk,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
 
-       writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
+       writel(cfg->perqspiclk,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERQSPICLK);
 
        /* Peri pernandsdmmcclk */
        writel(cfg->mainnandsdmmcclk,
-              &clock_manager_base->main_pll.mainnandsdmmcclk);
+              socfpga_get_clkmgr_addr() +
+              CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
 
        writel(cfg->pernandsdmmcclk,
-              &clock_manager_base->per_pll.pernandsdmmcclk);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
 
        /* Peri perbaseclk */
-       writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
+       writel(cfg->perbaseclk,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK);
 
        /* Peri s2fuser1clk */
-       writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
+       writel(cfg->s2fuser1clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_S2FUSER1CLK);
 
        /* 7 us must have elapsed before we can enable the VCO */
        while (timer_get_us() < end)
@@ -191,101 +202,112 @@ int cm_basic_init(const struct cm_config * const cfg)
        /* Enable vco */
        /* main pll vco */
        writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-              &clock_manager_base->main_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
 
        /* periferal pll */
        writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-              &clock_manager_base->per_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
 
        /* sdram pll vco */
        writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-              &clock_manager_base->sdr_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
        /* L3 MP and L3 SP */
-       writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
+       writel(cfg->maindiv,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV);
 
-       writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
+       writel(cfg->dbgdiv,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGDIV);
 
-       writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
+       writel(cfg->tracediv,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_TRACEDIV);
 
        /* L4 MP, L4 SP, can0, and can1 */
-       writel(cfg->perdiv, &clock_manager_base->per_pll.div);
+       writel(cfg->perdiv,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_DIV);
 
-       writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+       writel(cfg->gpiodiv,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_GPIODIV);
 
        cm_wait_for_lock(LOCKED_MASK);
 
        /* write the sdram clock counters before toggling outreset all */
        writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
-              &clock_manager_base->sdr_pll.ddrdqsclk);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
 
        writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
-              &clock_manager_base->sdr_pll.ddr2xdqsclk);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK);
 
        writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
-              &clock_manager_base->sdr_pll.ddrdqclk);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQCLK);
 
        writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
-              &clock_manager_base->sdr_pll.s2fuser2clk);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK);
 
        /*
         * after locking, but before taking out of bypass
         * assert/deassert outresetall
         */
-       u32 mainvco = readl(&clock_manager_base->main_pll.vco);
+       u32 mainvco = readl(socfpga_get_clkmgr_addr() +
+                           CLKMGR_GEN5_MAINPLL_VCO);
 
        /* assert main outresetall */
        writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->main_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
 
-       u32 periphvco = readl(&clock_manager_base->per_pll.vco);
+       u32 periphvco = readl(socfpga_get_clkmgr_addr() +
+                             CLKMGR_GEN5_PERPLL_VCO);
 
        /* assert pheriph outresetall */
        writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->per_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
 
        /* assert sdram outresetall */
-       writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
-               CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
-               &clock_manager_base->sdr_pll.vco);
+       writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN |
+              CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
        /* deassert main outresetall */
        writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->main_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
 
        /* deassert pheriph outresetall */
        writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
-              &clock_manager_base->per_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
 
        /* deassert sdram outresetall */
        writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-              &clock_manager_base->sdr_pll.vco);
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
 
        /*
         * now that we've toggled outreset all, all the clocks
         * are aligned nicely; so we can change any phase.
         */
        ret = cm_write_with_phase(cfg->ddrdqsclk,
-                                 &clock_manager_base->sdr_pll.ddrdqsclk,
+                                 (const void *)(socfpga_get_clkmgr_addr() +
+                                 CLKMGR_GEN5_SDRPLL_DDRDQSCLK),
                                  CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
        if (ret)
                return ret;
 
        /* SDRAM DDR2XDQSCLK */
        ret = cm_write_with_phase(cfg->ddr2xdqsclk,
-                                 &clock_manager_base->sdr_pll.ddr2xdqsclk,
+                                 (const void *)(socfpga_get_clkmgr_addr() +
+                                 CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK),
                                  CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
        if (ret)
                return ret;
 
        ret = cm_write_with_phase(cfg->ddrdqclk,
-                                 &clock_manager_base->sdr_pll.ddrdqclk,
+                                 (const void *)(socfpga_get_clkmgr_addr() +
+                                 CLKMGR_GEN5_SDRPLL_DDRDQCLK),
                                  CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
        if (ret)
                return ret;
 
        ret = cm_write_with_phase(cfg->s2fuser2clk,
-                                 &clock_manager_base->sdr_pll.s2fuser2clk,
+                                 (const void *)(socfpga_get_clkmgr_addr() +
+                                 CLKMGR_GEN5_SDRPLL_S2FUSER2CLK),
                                  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
        if (ret)
                return ret;
@@ -294,24 +316,28 @@ int cm_basic_init(const struct cm_config * const cfg)
        cm_write_bypass(0);
 
        /* clear safe mode */
-       cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
+       cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL) |
+                     CLKMGR_CTRL_SAFEMODE);
 
        /*
         * now that safe mode is clear with clocks gated
         * it safe to change the source mux for the flashes the the L4_MAIN
         */
-       writel(cfg->persrc, &clock_manager_base->per_pll.src);
-       writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
+       writel(cfg->persrc,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
+       writel(cfg->l4src,
+              socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
 
        /* Now ungate non-hw-managed clocks */
-       writel(~0, &clock_manager_base->main_pll.en);
-       writel(~0, &clock_manager_base->per_pll.en);
-       writel(~0, &clock_manager_base->sdr_pll.en);
+       writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN);
+       writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
+       writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN);
 
        /* Clear the loss of lock bits (write 1 to clear) */
-       writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
-              CLKMGR_INTER_MAINPLLLOST_MASK,
-              &clock_manager_base->inter);
+       writel(CLKMGR_INTER_SDRPLLLOST_MASK |
+                     CLKMGR_INTER_PERPLLLOST_MASK |
+                     CLKMGR_INTER_MAINPLLLOST_MASK,
+                     socfpga_get_clkmgr_addr() + CLKMGR_GEN5_INTER);
 
        return 0;
 }
@@ -321,7 +347,7 @@ static unsigned int cm_get_main_vco_clk_hz(void)
        u32 reg, clock;
 
        /* get the main VCO clock */
-       reg = readl(&clock_manager_base->main_pll.vco);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
        clock = cm_get_osc_clk_hz(1);
        clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
                  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
@@ -336,7 +362,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
        u32 reg, clock = 0;
 
        /* identify PER PLL clock source */
-       reg = readl(&clock_manager_base->per_pll.vco);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
        reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
              CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
        if (reg == CLKMGR_VCO_SSRC_EOSC1)
@@ -347,7 +373,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
                clock = cm_get_f2s_per_ref_clk_hz();
 
        /* get the PER VCO clock */
-       reg = readl(&clock_manager_base->per_pll.vco);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
        clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
                  CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
        clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
@@ -363,9 +389,9 @@ unsigned long cm_get_mpu_clk_hz(void)
        clock = cm_get_main_vco_clk_hz();
 
        /* get the MPU clock */
-       reg = readl(&clock_manager_base->altera.mpuclk);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK);
        clock /= (reg + 1);
-       reg = readl(&clock_manager_base->main_pll.mpuclk);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK);
        clock /= (reg + 1);
        return clock;
 }
@@ -375,7 +401,7 @@ unsigned long cm_get_sdram_clk_hz(void)
        u32 reg, clock = 0;
 
        /* identify SDRAM PLL clock source */
-       reg = readl(&clock_manager_base->sdr_pll.vco);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
        reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
              CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
        if (reg == CLKMGR_VCO_SSRC_EOSC1)
@@ -386,14 +412,14 @@ unsigned long cm_get_sdram_clk_hz(void)
                clock = cm_get_f2s_sdr_ref_clk_hz();
 
        /* get the SDRAM VCO clock */
-       reg = readl(&clock_manager_base->sdr_pll.vco);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
        clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
                  CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
        clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
                  CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
 
        /* get the SDRAM (DDR_DQS) clock */
-       reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
        reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
              CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
        clock /= (reg + 1);
@@ -406,7 +432,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
        u32 reg, clock = 0;
 
        /* identify the source of L4 SP clock */
-       reg = readl(&clock_manager_base->main_pll.l4src);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
        reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
              CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
 
@@ -414,20 +440,23 @@ unsigned int cm_get_l4_sp_clk_hz(void)
                clock = cm_get_main_vco_clk_hz();
 
                /* get the clock prior L4 SP divider (main clk) */
-               reg = readl(&clock_manager_base->altera.mainclk);
+               reg = readl(socfpga_get_clkmgr_addr() +
+                           CLKMGR_GEN5_ALTR_MAINCLK);
                clock /= (reg + 1);
-               reg = readl(&clock_manager_base->main_pll.mainclk);
+               reg = readl(socfpga_get_clkmgr_addr() +
+                           CLKMGR_GEN5_MAINPLL_MAINCLK);
                clock /= (reg + 1);
        } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
                clock = cm_get_per_vco_clk_hz();
 
                /* get the clock prior L4 SP divider (periph_base_clk) */
-               reg = readl(&clock_manager_base->per_pll.perbaseclk);
+               reg = readl(socfpga_get_clkmgr_addr() +
+                           CLKMGR_GEN5_PERPLL_PERBASECLK);
                clock /= (reg + 1);
        }
 
        /* get the L4 SP clock which supplied to UART */
-       reg = readl(&clock_manager_base->main_pll.maindiv);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV);
        reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
              CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
        clock = clock / (1 << reg);
@@ -440,7 +469,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
        u32 reg, clock = 0;
 
        /* identify the source of MMC clock */
-       reg = readl(&clock_manager_base->per_pll.src);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
        reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
              CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
 
@@ -450,13 +479,15 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
                clock = cm_get_main_vco_clk_hz();
 
                /* get the SDMMC clock */
-               reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
+               reg = readl(socfpga_get_clkmgr_addr() +
+                           CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
                clock /= (reg + 1);
        } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
                clock = cm_get_per_vco_clk_hz();
 
                /* get the SDMMC clock */
-               reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
+               reg = readl(socfpga_get_clkmgr_addr() +
+                           CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
                clock /= (reg + 1);
        }
 
@@ -470,7 +501,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
        u32 reg, clock = 0;
 
        /* identify the source of QSPI clock */
-       reg = readl(&clock_manager_base->per_pll.src);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
        reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
              CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
 
@@ -480,13 +511,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
                clock = cm_get_main_vco_clk_hz();
 
                /* get the qspi clock */
-               reg = readl(&clock_manager_base->main_pll.mainqspiclk);
+               reg = readl(socfpga_get_clkmgr_addr() +
+                           CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
                clock /= (reg + 1);
        } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
                clock = cm_get_per_vco_clk_hz();
 
                /* get the qspi clock */
-               reg = readl(&clock_manager_base->per_pll.perqspiclk);
+               reg = readl(socfpga_get_clkmgr_addr() +
+                           CLKMGR_GEN5_PERPLL_PERQSPICLK);
                clock /= (reg + 1);
        }
 
@@ -500,7 +533,7 @@ unsigned int cm_get_spi_controller_clk_hz(void)
        clock = cm_get_per_vco_clk_hz();
 
        /* get the clock prior L4 SP divider (periph_base_clk) */
-       reg = readl(&clock_manager_base->per_pll.perbaseclk);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK);
        clock /= (reg + 1);
 
        return clock;
index 8881703..5edeab1 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
 /*
  * function to write the bypass register which requires a poll of the
  * busy bit
  */
 static void cm_write_bypass_mainpll(u32 val)
 {
-       writel(val, &clock_manager_base->main_pll.bypass);
+       writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_BYPASS);
        cm_wait_for_fsm();
 }
 
 static void cm_write_bypass_perpll(u32 val)
 {
-       writel(val, &clock_manager_base->per_pll.bypass);
+       writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_BYPASS);
        cm_wait_for_fsm();
 }
 
 /* function to write the ctrl register which requires a poll of the busy bit */
 static void cm_write_ctrl(u32 val)
 {
-       writel(val, &clock_manager_base->ctrl);
+       writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL);
        cm_wait_for_fsm();
 }
 
@@ -66,12 +63,17 @@ void cm_basic_init(const struct cm_config * const cfg)
 
        writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
                ~CLKMGR_PLLGLOB_RST_MASK),
-               &clock_manager_base->main_pll.pllglob);
-       writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);
-       writel(vcocalib, &clock_manager_base->main_pll.vcocalib);
-       writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);
-       writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);
-       writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);
+               socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
+       writel(cfg->main_pll_fdbck,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
+       writel(vcocalib,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_VCOCALIB);
+       writel(cfg->main_pll_pllc0,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC0);
+       writel(cfg->main_pll_pllc1,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC1);
+       writel(cfg->main_pll_nocdiv,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCDIV);
 
        /* setup peripheral PLL dividers */
        /* calculate the vcocalib value */
@@ -88,18 +90,24 @@ void cm_basic_init(const struct cm_config * const cfg)
 
        writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
                ~CLKMGR_PLLGLOB_RST_MASK),
-               &clock_manager_base->per_pll.pllglob);
-       writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);
-       writel(vcocalib, &clock_manager_base->per_pll.vcocalib);
-       writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);
-       writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);
-       writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);
-       writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+               socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
+       writel(cfg->per_pll_fdbck,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
+       writel(vcocalib,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_VCOCALIB);
+       writel(cfg->per_pll_pllc0,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC0);
+       writel(cfg->per_pll_pllc1,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC1);
+       writel(cfg->per_pll_emacctl,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EMACCTL);
+       writel(cfg->per_pll_gpiodiv,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_GPIODIV);
 
        /* Take both PLL out of reset and power up */
-       setbits_le32(&clock_manager_base->main_pll.pllglob,
+       setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB,
                     CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
-       setbits_le32(&clock_manager_base->per_pll.pllglob,
+       setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB,
                     CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
 
 #define LOCKED_MASK \
@@ -113,66 +121,85 @@ void cm_basic_init(const struct cm_config * const cfg)
         * only take effect upon value change, we shall set a maximum value as
         * default value.
         */
-       writel(0xff, &clock_manager_base->main_pll.mpuclk);
-       writel(0xff, &clock_manager_base->main_pll.nocclk);
-       writel(0xff, &clock_manager_base->main_pll.cntr2clk);
-       writel(0xff, &clock_manager_base->main_pll.cntr3clk);
-       writel(0xff, &clock_manager_base->main_pll.cntr4clk);
-       writel(0xff, &clock_manager_base->main_pll.cntr5clk);
-       writel(0xff, &clock_manager_base->main_pll.cntr6clk);
-       writel(0xff, &clock_manager_base->main_pll.cntr7clk);
-       writel(0xff, &clock_manager_base->main_pll.cntr8clk);
-       writel(0xff, &clock_manager_base->main_pll.cntr9clk);
-       writel(0xff, &clock_manager_base->per_pll.cntr2clk);
-       writel(0xff, &clock_manager_base->per_pll.cntr3clk);
-       writel(0xff, &clock_manager_base->per_pll.cntr4clk);
-       writel(0xff, &clock_manager_base->per_pll.cntr5clk);
-       writel(0xff, &clock_manager_base->per_pll.cntr6clk);
-       writel(0xff, &clock_manager_base->per_pll.cntr7clk);
-       writel(0xff, &clock_manager_base->per_pll.cntr8clk);
-       writel(0xff, &clock_manager_base->per_pll.cntr9clk);
-
-       writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);
-       writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);
-       writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);
-       writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);
-       writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);
-       writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);
-       writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);
-       writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);
-       writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);
-       writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);
-       writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);
-       writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);
-       writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);
-       writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);
-       writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);
-       writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);
-       writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);
-       writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
+       writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
+
+       writel(cfg->main_pll_mpuclk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
+       writel(cfg->main_pll_nocclk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
+       writel(cfg->main_pll_cntr2clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
+       writel(cfg->main_pll_cntr3clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
+       writel(cfg->main_pll_cntr4clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
+       writel(cfg->main_pll_cntr5clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
+       writel(cfg->main_pll_cntr6clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
+       writel(cfg->main_pll_cntr7clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
+       writel(cfg->main_pll_cntr8clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
+       writel(cfg->main_pll_cntr9clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
+       writel(cfg->per_pll_cntr2clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
+       writel(cfg->per_pll_cntr3clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
+       writel(cfg->per_pll_cntr4clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
+       writel(cfg->per_pll_cntr5clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
+       writel(cfg->per_pll_cntr6clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
+       writel(cfg->per_pll_cntr7clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
+       writel(cfg->per_pll_cntr8clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
+       writel(cfg->per_pll_cntr9clk,
+              socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
 
        /* Take all PLLs out of bypass */
        cm_write_bypass_mainpll(0);
        cm_write_bypass_perpll(0);
 
        /* clear safe mode / out of boot mode */
-       cm_write_ctrl(readl(&clock_manager_base->ctrl)
-                       & ~(CLKMGR_CTRL_SAFEMODE));
+       cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL) &
+                     ~(CLKMGR_CTRL_SAFEMODE));
 
        /* Now ungate non-hw-managed clocks */
-       writel(~0, &clock_manager_base->main_pll.en);
-       writel(~0, &clock_manager_base->per_pll.en);
+       writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_EN);
+       writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EN);
 
        /* Clear the loss of lock bits (write 1 to clear) */
-       writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,
-              &clock_manager_base->intrclr);
+       writel(CLKMGR_INTER_PERPLLLOST_MASK |
+                     CLKMGR_INTER_MAINPLLLOST_MASK,
+                     socfpga_get_clkmgr_addr() + CLKMGR_S10_INTRCLR);
 }
 
 static unsigned long cm_get_main_vco_clk_hz(void)
 {
         unsigned long fref, refdiv, mdiv, reg, vco;
 
-       reg = readl(&clock_manager_base->main_pll.pllglob);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
 
        fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
                CLKMGR_PLLGLOB_VCO_PSRC_MASK;
@@ -191,7 +218,7 @@ static unsigned long cm_get_main_vco_clk_hz(void)
        refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
                  CLKMGR_PLLGLOB_REFCLKDIV_MASK;
 
-       reg = readl(&clock_manager_base->main_pll.fdbck);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
        mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
 
        vco = fref / refdiv;
@@ -203,7 +230,7 @@ static unsigned long cm_get_per_vco_clk_hz(void)
 {
        unsigned long fref, refdiv, mdiv, reg, vco;
 
-       reg = readl(&clock_manager_base->per_pll.pllglob);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
 
        fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
                CLKMGR_PLLGLOB_VCO_PSRC_MASK;
@@ -222,7 +249,7 @@ static unsigned long cm_get_per_vco_clk_hz(void)
        refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
                  CLKMGR_PLLGLOB_REFCLKDIV_MASK;
 
-       reg = readl(&clock_manager_base->per_pll.fdbck);
+       reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
        mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
 
        vco = fref / refdiv;
@@ -232,20 +259,23 @@ static unsigned long cm_get_per_vco_clk_hz(void)
 
 unsigned long cm_get_mpu_clk_hz(void)
 {
-       unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);
+       unsigned long clock = readl(socfpga_get_clkmgr_addr() +
+                                   CLKMGR_S10_MAINPLL_MPUCLK);
 
        clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
 
        switch (clock) {
        case CLKMGR_CLKSRC_MAIN:
                clock = cm_get_main_vco_clk_hz();
-               clock /= (readl(&clock_manager_base->main_pll.pllc0) &
+               clock /= (readl(socfpga_get_clkmgr_addr() +
+                               CLKMGR_S10_MAINPLL_PLLC0) &
                          CLKMGR_PLLC0_DIV_MASK);
                break;
 
        case CLKMGR_CLKSRC_PER:
                clock = cm_get_per_vco_clk_hz();
-               clock /= (readl(&clock_manager_base->per_pll.pllc0) &
+               clock /= (readl(socfpga_get_clkmgr_addr() +
+                               CLKMGR_S10_PERPLL_PLLC0) &
                          CLKMGR_CLKCNT_MSK);
                break;
 
@@ -262,28 +292,30 @@ unsigned long cm_get_mpu_clk_hz(void)
                break;
        }
 
-       clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
-               CLKMGR_CLKCNT_MSK);
+       clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+                           CLKMGR_S10_MAINPLL_MPUCLK) & CLKMGR_CLKCNT_MSK);
        return clock;
 }
 
 unsigned int cm_get_l3_main_clk_hz(void)
 {
-       u32 clock = readl(&clock_manager_base->main_pll.nocclk);
+       u32 clock = readl(socfpga_get_clkmgr_addr() +
+                         CLKMGR_S10_MAINPLL_NOCCLK);
 
        clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
 
        switch (clock) {
        case CLKMGR_CLKSRC_MAIN:
                clock = cm_get_main_vco_clk_hz();
-               clock /= (readl(&clock_manager_base->main_pll.pllc1) &
+               clock /= (readl(socfpga_get_clkmgr_addr() +
+                               CLKMGR_S10_MAINPLL_PLLC1) &
                          CLKMGR_PLLC0_DIV_MASK);
                break;
 
        case CLKMGR_CLKSRC_PER:
                clock = cm_get_per_vco_clk_hz();
-               clock /= (readl(&clock_manager_base->per_pll.pllc1) &
-                         CLKMGR_CLKCNT_MSK);
+               clock /= (readl(socfpga_get_clkmgr_addr() +
+                         CLKMGR_S10_PERPLL_PLLC1) & CLKMGR_CLKCNT_MSK);
                break;
 
        case CLKMGR_CLKSRC_OSC1:
@@ -299,28 +331,31 @@ unsigned int cm_get_l3_main_clk_hz(void)
                break;
        }
 
-       clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
-               CLKMGR_CLKCNT_MSK);
+       clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+                     CLKMGR_S10_MAINPLL_NOCCLK) & CLKMGR_CLKCNT_MSK);
        return clock;
 }
 
 unsigned int cm_get_mmc_controller_clk_hz(void)
 {
-       u32 clock = readl(&clock_manager_base->per_pll.cntr6clk);
+       u32 clock = readl(socfpga_get_clkmgr_addr() +
+                         CLKMGR_S10_PERPLL_CNTR6CLK);
 
        clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
 
        switch (clock) {
        case CLKMGR_CLKSRC_MAIN:
                clock = cm_get_l3_main_clk_hz();
-               clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
-                       CLKMGR_CLKCNT_MSK);
+               clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+                                   CLKMGR_S10_MAINPLL_CNTR6CLK) &
+                             CLKMGR_CLKCNT_MSK);
                break;
 
        case CLKMGR_CLKSRC_PER:
                clock = cm_get_l3_main_clk_hz();
-               clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
-                       CLKMGR_CLKCNT_MSK);
+               clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
+                                   CLKMGR_S10_PERPLL_CNTR6CLK) &
+                             CLKMGR_CLKCNT_MSK);
                break;
 
        case CLKMGR_CLKSRC_OSC1:
@@ -342,8 +377,9 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 {
        u32 clock = cm_get_l3_main_clk_hz();
 
-       clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
-                 CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
+       clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
+                              CLKMGR_S10_MAINPLL_NOCDIV) >>
+                        CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
        return clock;
 }
 
@@ -356,8 +392,9 @@ unsigned int cm_get_spi_controller_clk_hz(void)
 {
        u32 clock = cm_get_l3_main_clk_hz();
 
-       clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
-                 CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
+       clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
+                              CLKMGR_S10_MAINPLL_NOCDIV) >>
+                        CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
        return clock;
 }
 
index dd80e3a..6de7cae 100644 (file)
@@ -6,6 +6,8 @@
 #ifndef _CLOCK_MANAGER_H_
 #define _CLOCK_MANAGER_H_
 
+phys_addr_t socfpga_get_clkmgr_addr(void);
+
 #ifndef __ASSEMBLER__
 void cm_wait_for_lock(u32 mask);
 int cm_wait_for_fsm(void);
index de8c225..23f280d 100644 (file)
@@ -8,86 +8,57 @@
 
 #ifndef __ASSEMBLER__
 
-struct socfpga_clock_manager_main_pll {
-       u32  vco0;
-       u32  vco1;
-       u32  en;
-       u32  ens;
-       u32  enr;
-       u32  bypass;
-       u32  bypasss;
-       u32  bypassr;
-       u32  mpuclk;
-       u32  nocclk;
-       u32  cntr2clk;
-       u32  cntr3clk;
-       u32  cntr4clk;
-       u32  cntr5clk;
-       u32  cntr6clk;
-       u32  cntr7clk;
-       u32  cntr8clk;
-       u32  cntr9clk;
-       u32  pad_0x48_0x5b[5];
-       u32  cntr15clk;
-       u32  outrst;
-       u32  outrststat;
-       u32  nocdiv;
-       u32  pad_0x6c_0x80[5];
-};
-
-struct socfpga_clock_manager_per_pll {
-       u32  vco0;
-       u32  vco1;
-       u32  en;
-       u32  ens;
-       u32  enr;
-       u32  bypass;
-       u32  bypasss;
-       u32  bypassr;
-       u32  pad_0x20_0x27[2];
-       u32  cntr2clk;
-       u32  cntr3clk;
-       u32  cntr4clk;
-       u32  cntr5clk;
-       u32  cntr6clk;
-       u32  cntr7clk;
-       u32  cntr8clk;
-       u32  cntr9clk;
-       u32  pad_0x48_0x5f[6];
-       u32  outrst;
-       u32  outrststat;
-       u32  emacctl;
-       u32  gpiodiv;
-       u32  pad_0x70_0x80[4];
-};
-
-struct socfpga_clock_manager_altera {
-       u32     mpuclk;
-       u32     nocclk;
-       u32     mainmisc0;
-       u32     mainmisc1;
-       u32     perimisc0;
-       u32     perimisc1;
-};
-
-struct socfpga_clock_manager {
-       /* clkmgr */
-       u32  ctrl;
-       u32  intr;
-       u32  intrs;
-       u32  intrr;
-       u32  intren;
-       u32  intrens;
-       u32  intrenr;
-       u32  stat;
-       u32  testioctrl;
-       u32  _pad_0x24_0x40[7];
-       /* mainpllgrp */
-       struct socfpga_clock_manager_main_pll main_pll;
-       /* perpllgrp */
-       struct socfpga_clock_manager_per_pll per_pll;
-       struct socfpga_clock_manager_altera altera;
-};
+/* Clock manager group */
+#define CLKMGR_A10_CTRL                                0x00
+#define CLKMGR_A10_INTR                                0x04
+#define CLKMGR_A10_STAT                                0x1c
+/* MainPLL group */
+#define CLKMGR_A10_MAINPLL_VCO0                        0x40
+#define CLKMGR_A10_MAINPLL_VCO1                        0x44
+#define CLKMGR_A10_MAINPLL_EN                  0x48
+#define CLKMGR_A10_MAINPLL_ENS                 0x4c
+#define CLKMGR_A10_MAINPLL_ENR                 0x50
+#define CLKMGR_A10_MAINPLL_BYPASS              0x54
+#define CLKMGR_A10_MAINPLL_BYPASSS             0x58
+#define CLKMGR_A10_MAINPLL_BYPASSR             0x5c
+#define CLKMGR_A10_MAINPLL_MPUCLK              0x60
+#define CLKMGR_A10_MAINPLL_NOCCLK              0x64
+#define CLKMGR_A10_MAINPLL_CNTR2CLK            0x68
+#define CLKMGR_A10_MAINPLL_CNTR3CLK            0x6c
+#define CLKMGR_A10_MAINPLL_CNTR4CLK            0x70
+#define CLKMGR_A10_MAINPLL_CNTR5CLK            0x74
+#define CLKMGR_A10_MAINPLL_CNTR6CLK            0x78
+#define CLKMGR_A10_MAINPLL_CNTR7CLK            0x7c
+#define CLKMGR_A10_MAINPLL_CNTR8CLK            0x80
+#define CLKMGR_A10_MAINPLL_CNTR9CLK            0x84
+#define CLKMGR_A10_MAINPLL_CNTR15CLK           0x9c
+#define CLKMGR_A10_MAINPLL_NOCDIV              0xa8
+/* Peripheral PLL group */
+#define CLKMGR_A10_PERPLL_VCO0                 0xc0
+#define CLKMGR_A10_PERPLL_VCO1                 0xc4
+#define CLKMGR_A10_PERPLL_EN                   0xc8
+#define CLKMGR_A10_PERPLL_ENS                  0xcc
+#define CLKMGR_A10_PERPLL_ENR                  0xd0
+#define CLKMGR_A10_PERPLL_BYPASS               0xd4
+#define CLKMGR_A10_PERPLL_BYPASSS              0xd8
+#define CLKMGR_A10_PERPLL_BYPASSR              0xdc
+#define CLKMGR_A10_PERPLL_CNTR2CLK             0xe8
+#define CLKMGR_A10_PERPLL_CNTR3CLK             0xec
+#define CLKMGR_A10_PERPLL_CNTR4CLK             0xf0
+#define CLKMGR_A10_PERPLL_CNTR5CLK             0xf4
+#define CLKMGR_A10_PERPLL_CNTR6CLK             0xf8
+#define CLKMGR_A10_PERPLL_CNTR7CLK             0xfc
+#define CLKMGR_A10_PERPLL_CNTR8CLK             0x100
+#define CLKMGR_A10_PERPLL_CNTR9CLK             0x104
+#define CLKMGR_A10_PERPLL_EMACCTL              0x128
+#define CLKMGR_A10_PERPLL_GPIOFIV              0x12c
+/* Altera group */
+#define CLKMGR_A10_ALTR_MPUCLK                 0x140
+#define CLKMGR_A10_ALTR_NOCCLK                 0x144
+
+#define CLKMGR_STAT                            CLKMGR_A10_STAT
+#define CLKMGR_INTER                           CLKMGR_A10_INTER
+#define CLKMGR_PERPLL_EN                       CLKMGR_A10_PERPLL_EN
 
 #ifdef CONFIG_SPL_BUILD
 int cm_basic_init(const void *blob);
@@ -100,8 +71,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 
 #endif /* __ASSEMBLER__ */
 
-#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET                        0x140
-#define CLKMGR_MAINPLL_NOC_CLK_OFFSET                  0x144
 #define LOCKED_MASK    (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
                         CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
 
index 5bedf28..0865509 100644 (file)
@@ -45,71 +45,53 @@ struct cm_config {
        u32 altera_grp_mpuclk;
 };
 
-struct socfpga_clock_manager_main_pll {
-       u32     vco;
-       u32     misc;
-       u32     mpuclk;
-       u32     mainclk;
-       u32     dbgatclk;
-       u32     mainqspiclk;
-       u32     mainnandsdmmcclk;
-       u32     cfgs2fuser0clk;
-       u32     en;
-       u32     maindiv;
-       u32     dbgdiv;
-       u32     tracediv;
-       u32     l4src;
-       u32     stat;
-       u32     _pad_0x38_0x40[2];
-};
-
-struct socfpga_clock_manager_per_pll {
-       u32     vco;
-       u32     misc;
-       u32     emac0clk;
-       u32     emac1clk;
-       u32     perqspiclk;
-       u32     pernandsdmmcclk;
-       u32     perbaseclk;
-       u32     s2fuser1clk;
-       u32     en;
-       u32     div;
-       u32     gpiodiv;
-       u32     src;
-       u32     stat;
-       u32     _pad_0x34_0x40[3];
-};
-
-struct socfpga_clock_manager_sdr_pll {
-       u32     vco;
-       u32     ctrl;
-       u32     ddrdqsclk;
-       u32     ddr2xdqsclk;
-       u32     ddrdqclk;
-       u32     s2fuser2clk;
-       u32     en;
-       u32     stat;
-};
-
-struct socfpga_clock_manager_altera {
-       u32     mpuclk;
-       u32     mainclk;
-};
-
-struct socfpga_clock_manager {
-       u32     ctrl;
-       u32     bypass;
-       u32     inter;
-       u32     intren;
-       u32     dbctrl;
-       u32     stat;
-       u32     _pad_0x18_0x3f[10];
-       struct socfpga_clock_manager_main_pll main_pll;
-       struct socfpga_clock_manager_per_pll per_pll;
-       struct socfpga_clock_manager_sdr_pll sdr_pll;
-       struct socfpga_clock_manager_altera altera;
-       u32     _pad_0xe8_0x200[70];
-};
+/* Clock manager group */
+#define CLKMGR_GEN5_CTRL                       0x00
+#define CLKMGR_GEN5_BYPASS                     0x04
+#define CLKMGR_GEN5_INTER                      0x08
+#define CLKMGR_GEN5_STAT                       0x14
+/* MainPLL group */
+#define CLKMGR_GEN5_MAINPLL_VCO                        0x40
+#define CLKMGR_GEN5_MAINPLL_MISC               0x44
+#define CLKMGR_GEN5_MAINPLL_MPUCLK             0x48
+#define CLKMGR_GEN5_MAINPLL_MAINCLK            0x4c
+#define CLKMGR_GEN5_MAINPLL_DBGATCLK           0x50
+#define CLKMGR_GEN5_MAINPLL_MAINQSPICLK                0x54
+#define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK   0x58
+#define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK     0x5c
+#define CLKMGR_GEN5_MAINPLL_EN                 0x60
+#define CLKMGR_GEN5_MAINPLL_MAINDIV            0x64
+#define CLKMGR_GEN5_MAINPLL_DBGDIV             0x68
+#define CLKMGR_GEN5_MAINPLL_TRACEDIV           0x6c
+#define CLKMGR_GEN5_MAINPLL_L4SRC              0x70
+/* Peripheral PLL group */
+#define CLKMGR_GEN5_PERPLL_VCO                 0x80
+#define CLKMGR_GEN5_PERPLL_MISC                        0x84
+#define CLKMGR_GEN5_PERPLL_EMAC0CLK            0x88
+#define CLKMGR_GEN5_PERPLL_EMAC1CLK            0x8c
+#define CLKMGR_GEN5_PERPLL_PERQSPICLK          0x90
+#define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK     0x94
+#define CLKMGR_GEN5_PERPLL_PERBASECLK          0x98
+#define CLKMGR_GEN5_PERPLL_S2FUSER1CLK         0x9c
+#define CLKMGR_GEN5_PERPLL_EN                  0xa0
+#define CLKMGR_GEN5_PERPLL_DIV                 0xa4
+#define CLKMGR_GEN5_PERPLL_GPIODIV             0xa8
+#define CLKMGR_GEN5_PERPLL_SRC                 0xac
+/* SDRAM PLL group */
+#define CLKMGR_GEN5_SDRPLL_VCO                 0xc0
+#define CLKMGR_GEN5_SDRPLL_CTRL                        0xc4
+#define CLKMGR_GEN5_SDRPLL_DDRDQSCLK           0xc8
+#define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK         0xcc
+#define CLKMGR_GEN5_SDRPLL_DDRDQCLK            0xd0
+#define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK         0xd4
+#define CLKMGR_GEN5_SDRPLL_EN                  0xd8
+/* Altera group */
+#define CLKMGR_GEN5_ALTR_MPUCLK                        0xe0
+#define CLKMGR_GEN5_ALTR_MAINCLK               0xe4
+
+#define CLKMGR_STAT                            CLKMGR_GEN5_STAT
+#define CLKMGR_INTER                           CLKMGR_GEN5_INTER
+#define CLKMGR_PERPLL_EN                       CLKMGR_GEN5_PERPLL_EN
 
 /* Clock speed accessors */
 unsigned long cm_get_mpu_clk_hz(void);
index 24b20de..13eb235 100644 (file)
@@ -69,75 +69,54 @@ struct cm_config {
 
 void cm_basic_init(const struct cm_config * const cfg);
 
-struct socfpga_clock_manager_main_pll {
-       u32     en;
-       u32     ens;
-       u32     enr;
-       u32     bypass;
-       u32     bypasss;
-       u32     bypassr;
-       u32     mpuclk;
-       u32     nocclk;
-       u32     cntr2clk;
-       u32     cntr3clk;
-       u32     cntr4clk;
-       u32     cntr5clk;
-       u32     cntr6clk;
-       u32     cntr7clk;
-       u32     cntr8clk;
-       u32     cntr9clk;
-       u32     nocdiv;
-       u32     pllglob;
-       u32     fdbck;
-       u32     mem;
-       u32     memstat;
-       u32     pllc0;
-       u32     pllc1;
-       u32     vcocalib;
-       u32     _pad_0x90_0xA0[5];
-};
-
-struct socfpga_clock_manager_per_pll {
-       u32     en;
-       u32     ens;
-       u32     enr;
-       u32     bypass;
-       u32     bypasss;
-       u32     bypassr;
-       u32     cntr2clk;
-       u32     cntr3clk;
-       u32     cntr4clk;
-       u32     cntr5clk;
-       u32     cntr6clk;
-       u32     cntr7clk;
-       u32     cntr8clk;
-       u32     cntr9clk;
-       u32     emacctl;
-       u32     gpiodiv;
-       u32     pllglob;
-       u32     fdbck;
-       u32     mem;
-       u32     memstat;
-       u32     pllc0;
-       u32     pllc1;
-       u32     vcocalib;
-       u32     _pad_0x100_0x124[10];
-};
+/* Control status */
+#define CLKMGR_S10_CTRL                                        0x00
+#define CLKMGR_S10_STAT                                        0x04
+#define CLKMGR_S10_INTRCLR                             0x14
+/* Mainpll group */
+#define CLKMGR_S10_MAINPLL_EN                          0x30
+#define CLKMGR_S10_MAINPLL_BYPASS                      0x3c
+#define CLKMGR_S10_MAINPLL_MPUCLK                      0x48
+#define CLKMGR_S10_MAINPLL_NOCCLK                      0x4c
+#define CLKMGR_S10_MAINPLL_CNTR2CLK                    0x50
+#define CLKMGR_S10_MAINPLL_CNTR3CLK                    0x54
+#define CLKMGR_S10_MAINPLL_CNTR4CLK                    0x58
+#define CLKMGR_S10_MAINPLL_CNTR5CLK                    0x5c
+#define CLKMGR_S10_MAINPLL_CNTR6CLK                    0x60
+#define CLKMGR_S10_MAINPLL_CNTR7CLK                    0x64
+#define CLKMGR_S10_MAINPLL_CNTR8CLK                    0x68
+#define CLKMGR_S10_MAINPLL_CNTR9CLK                    0x6c
+#define CLKMGR_S10_MAINPLL_NOCDIV                      0x70
+#define CLKMGR_S10_MAINPLL_PLLGLOB                     0x74
+#define CLKMGR_S10_MAINPLL_FDBCK                       0x78
+#define CLKMGR_S10_MAINPLL_MEMSTAT                     0x80
+#define CLKMGR_S10_MAINPLL_PLLC0                       0x84
+#define CLKMGR_S10_MAINPLL_PLLC1                       0x88
+#define CLKMGR_S10_MAINPLL_VCOCALIB                    0x8c
+/* Periphpll group */
+#define CLKMGR_S10_PERPLL_EN                           0xa4
+#define CLKMGR_S10_PERPLL_BYPASS                       0xac
+#define CLKMGR_S10_PERPLL_CNTR2CLK                     0xbc
+#define CLKMGR_S10_PERPLL_CNTR3CLK                     0xc0
+#define CLKMGR_S10_PERPLL_CNTR4CLK                     0xc4
+#define CLKMGR_S10_PERPLL_CNTR5CLK                     0xc8
+#define CLKMGR_S10_PERPLL_CNTR6CLK                     0xcc
+#define CLKMGR_S10_PERPLL_CNTR7CLK                     0xd0
+#define CLKMGR_S10_PERPLL_CNTR8CLK                     0xd4
+#define CLKMGR_S10_PERPLL_CNTR9CLK                     0xd8
+#define CLKMGR_S10_PERPLL_EMACCTL                      0xdc
+#define CLKMGR_S10_PERPLL_GPIODIV                      0xe0
+#define CLKMGR_S10_PERPLL_PLLGLOB                      0xe4
+#define CLKMGR_S10_PERPLL_FDBCK                                0xe8
+#define CLKMGR_S10_PERPLL_MEMSTAT                      0xf0
+#define CLKMGR_S10_PERPLL_PLLC0                                0xf4
+#define CLKMGR_S10_PERPLL_PLLC1                                0xf8
+#define CLKMGR_S10_PERPLL_VCOCALIB                     0xfc
+
+#define CLKMGR_STAT                                    CLKMGR_S10_STAT
+#define CLKMGR_INTER                                   CLKMGR_S10_INTER
+#define CLKMGR_PERPLL_EN                               CLKMGR_S10_PERPLL_EN
 
-struct socfpga_clock_manager {
-       u32     ctrl;
-       u32     stat;
-       u32     testioctrl;
-       u32     intrgen;
-       u32     intrmsk;
-       u32     intrclr;
-       u32     intrsts;
-       u32     intrstk;
-       u32     intrraw;
-       u32     _pad_0x24_0x2c[3];
-       struct socfpga_clock_manager_main_pll main_pll;
-       struct socfpga_clock_manager_per_pll per_pll;
-};
 
 #define CLKMGR_CTRL_SAFEMODE                           BIT(0)
 #define CLKMGR_BYPASS_MAINPLL_ALL                      0x00000007
index 1ef02a1..b86ff96 100644 (file)
@@ -23,6 +23,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+phys_addr_t socfpga_clkmgr_base __section(".data");
 phys_addr_t socfpga_rstmgr_base __section(".data");
 phys_addr_t socfpga_sysmgr_base __section(".data");
 
@@ -243,6 +244,10 @@ void socfpga_get_managers_addr(void)
        ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
        if (ret)
                hang();
+
+       ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
+       if (ret)
+               hang();
 }
 
 phys_addr_t socfpga_get_rstmgr_addr(void)
@@ -254,3 +259,8 @@ phys_addr_t socfpga_get_sysmgr_addr(void)
 {
        return socfpga_sysmgr_base;
 }
+
+phys_addr_t socfpga_get_clkmgr_addr(void)
+{
+       return socfpga_clkmgr_base;
+}
index df9e8cc..568a3e7 100644 (file)
@@ -18,9 +18,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-               (void *)SOCFPGA_CLKMGR_ADDRESS;
-
 struct socfpga_dwmci_plat {
        struct mmc_config cfg;
        struct mmc mmc;
@@ -54,8 +51,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
                         ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
 
        /* Disable SDMMC clock. */
-       clrbits_le32(&clock_manager_base->per_pll.en,
-               CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+       clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+                    CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 
        debug("%s: drvsel %d smplsel %d\n", __func__,
              priv->drvsel, priv->smplsel);
@@ -65,8 +62,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
                readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
 
        /* Enable SDMMC clock */
-       setbits_le32(&clock_manager_base->per_pll.en,
-               CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+       setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+                    CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 }
 
 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)