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Blackfin arch: do not allow L2 to be cached on BF561 SMP
author
Mike Frysinger
<vapier.adi@gmail.com>
Wed, 7 Jan 2009 15:14:38 +0000
(23:14 +0800)
committer
Bryan Wu
<cooloney@kernel.org>
Wed, 7 Jan 2009 15:14:38 +0000
(23:14 +0800)
Signed-off-by: Bryan Wu <cooloney@kernel.org>
arch/blackfin/Kconfig
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diff --git
a/arch/blackfin/Kconfig
b/arch/blackfin/Kconfig
index
b8bc5a4
..
f8edfbe
100644
(file)
--- a/
arch/blackfin/Kconfig
+++ b/
arch/blackfin/Kconfig
@@
-866,7
+866,7
@@
endchoice
config BFIN_L2_CACHEABLE
bool "Cache L2 SRAM"
- depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x ||
BF561
)
+ depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x ||
(BF561 && !SMP)
)
default n
help
Select to make L2 SRAM cacheable in L1 data and instruction cache.