dts:starfive: Fix spi and qspi compilation warning
authorxingyu.wu <xingyu.wu@starfivetech.com>
Fri, 6 May 2022 07:52:26 +0000 (15:52 +0800)
committerxingyu.wu <xingyu.wu@starfivetech.com>
Sat, 7 May 2022 01:30:26 +0000 (09:30 +0800)
Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
arch/riscv/boot/dts/starfive/jh7110-common.dtsi [changed mode: 0644->0755]
arch/riscv/boot/dts/starfive/jh7110.dtsi
drivers/spi/spi-pl022.c

old mode 100644 (file)
new mode 100755 (executable)
index 488b98b..21d2a2b
@@ -12,7 +12,7 @@
        aliases {
                spi0="/soc/spi@13010000";
                gpio0="/soc/gpio@13040000";
-               ethernet0="/soc/gmac0@16030000";
+               ethernet0="/soc/ethernet@16030000";
                mmc0="/soc/sdio0@16010000";
                mmc1="/soc/sdio1@16020000";
        };
index 7cddd1d..7c75c1c 100755 (executable)
                        status = "disabled";
                };
 
-               qspi: qspi@13010000 {
-                       compatible = "cadence,qspi","cdns,qspi-nor";
+               qspi: spi@13010000 {
+                       compatible = "cdns,qspi-nor";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0x0 0x13010000 0x0 0x10000
                        status = "disabled";
                };
 
-               spi0: spi0@10060000 {
+               spi0: spi@10060000 {
                        compatible = "arm,pl022", "arm,primecell";
                        reg = <0x0 0x10060000 0x0 0x10000>;
                        clocks = <&clkgen JH7110_SPI0_CLK_APB>;
index 5e1ee45..633c460 100755 (executable)
@@ -2187,7 +2187,7 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
        pl022->rst = devm_reset_control_get_exclusive(&adev->dev, "rst_apb");
        if (!IS_ERR(pl022->rst)) {
                status = reset_control_deassert(pl022->rst);
-               if(status){
+               if (status) {
                        dev_err(&adev->dev, "could not deassert SSP/SPI bus reset\n");
                        goto err_no_rst_clr;
                }