"stg_apb", "clk_rtc",
"gmac0_rmii_refin", "gmac0_rgmii_rxin";
#clock-cells = <1>;
+ starfive,sys-syscon = <&sys_syscon 0x18 0x1c
+ 0x20 0x24 0x28 0x2c 0x30 0x34>;
status = "okay";
};
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VHOST_MENU is not set
CONFIG_GOLDFISH=y
+CONFIG_CLK_STARFIVE_JH7110_PLL=y
CONFIG_STARFIVE_TIMER=y
CONFIG_MAILBOX=y
CONFIG_STARFIVE_MBOX=m
help
Say yes here to support the isp clocks on the StarFive
JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_PLL
+ bool "StarFive JH7110 pll clock support"
+ depends on CLK_STARFIVE_JH7110
+ default y if SOC_STARFIVE_JH7110
+ help
+ Say yes here to support the pll clocks on the StarFive
+ JH7110 SoC and then change or read the pll clock's rate
+ through setting or reading the syscon registers and calculate.
clk-starfive-jh7110-stg.o \
clk-starfive-jh7110-aon.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
-obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
\ No newline at end of file
+obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o
#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
#include "clk-starfive-jh7110.h"
+/* external clocks */
+#define JH7110_OSC (JH7110_CLK_END + 0)
+/* aon external clocks */
+#define JH7110_GMAC0_RMII_REFIN (JH7110_CLK_END + 12)
+#define JH7110_GMAC0_RGMII_RXIN (JH7110_CLK_END + 13)
+#define JH7110_CLK_RTC (JH7110_CLK_END + 14)
+
static const struct jh7110_clk_data jh7110_clk_aon_data[] __initconst = {
//source
JH7110__DIV(JH7110_OSC_DIV4, "osc_div4", 4, JH7110_OSC),
JH7110_OSC_DIV4,
JH7110_OSC),
//gmac5
- JH7110_GATE(JH7110_U0_GMAC5_CLK_AHB,
+ JH7110_GATE(JH7110_U0_GMAC5_CLK_AHB,
"u0_dw_gmac5_axi64_clk_ahb",
GATE_FLAG_NORMAL, JH7110_AON_AHB),
JH7110_GATE(JH7110_U0_GMAC5_CLK_AXI,
.name = jh7110_clk_aon_data[idx].name,
.ops = starfive_jh7110_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH7110_CLK_MUX_MASK) \
- >> JH7110_CLK_MUX_SHIFT) + 1,
+ .num_parents = ((max & JH7110_CLK_MUX_MASK) >>
+ JH7110_CLK_MUX_SHIFT) + 1,
.flags = jh7110_clk_aon_data[idx].flags,
};
struct jh7110_clk *clk = &priv->reg[idx];
if (pidx < JH7110_CLK_REG_END)
parents[i].hw = &priv->reg[pidx].hw;
- else if ((pidx < JH7110_CLK_END) && \
+ else if ((pidx < JH7110_CLK_END) &&
(pidx > JH7110_RTC_HMS_CLK_CAL))
parents[i].hw = priv->pll[PLL_OF(pidx)];
+ else if (pidx == JH7110_OSC)
+ parents[i].fw_name = "osc";
else if (pidx == JH7110_GMAC0_RMII_REFIN)
parents[i].fw_name = "gmac0_rmii_refin";
else if (pidx == JH7110_GMAC0_RGMII_RXIN)
return ret;
}
- dev_dbg(&pdev->dev,"starfive JH7110 clk_aon init successfully.");
+ dev_dbg(&pdev->dev, "starfive JH7110 clk_aon init successfully.");
return 0;
}
#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
#include "clk-starfive-jh7110.h"
+#include "clk-starfive-jh7110-pll.h"
static struct jh7110_clk * __init jh7110_clk_from(struct clk_hw *hw)
{
struct jh7110_clk *clk = jh7110_clk_from(hw);
unsigned long parent = req->best_parent_rate;
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
- unsigned long div = min_t(unsigned long,
+ unsigned long div = min_t(unsigned long,
DIV_ROUND_UP(parent, rate), clk->max_div);
unsigned long result = parent / div;
}
EXPORT_SYMBOL_GPL(starfive_jh7110_clk_ops);
-static struct clk_hw *jh7110_clk_get(struct of_phandle_args *clkspec, void *data)
+static struct clk_hw *jh7110_clk_get(struct of_phandle_args *clkspec,
+ void *data)
{
struct jh7110_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_PLL0_OUT)
return &priv->reg[idx].hw;
- if (idx < JH7110_CLK_END)
+ if (idx < JH7110_CLK_END) {
+#ifdef CONFIG_CLK_STARFIVE_JH7110_PLL
+ if ((idx == JH7110_PLL0_OUT) || (idx == JH7110_PLL2_OUT))
+ return &priv->pll_priv[PLL_OF(idx)].hw;
+#endif
return priv->pll[PLL_OF(idx)];
+ }
return ERR_PTR(-EINVAL);
}
spin_lock_init(&priv->rmw_lock);
priv->dev = &pdev->dev;
+#ifdef CONFIG_CLK_STARFIVE_JH7110_PLL
+ ret = clk_starfive_jh7110_pll_init(pdev, priv->pll_priv);
+ if (ret)
+ return ret;
+#endif
+
ret = clk_starfive_jh7110_sys_init(pdev, priv);
if (ret)
return ret;
if (ret)
return ret;
- dev_info(&pdev->dev,"starfive JH7110 clkgen init successfully.");
+ dev_info(&pdev->dev, "starfive JH7110 clkgen init successfully.");
return 0;
}
-static const struct of_device_id clk_starfive_jh7110_match[] = {
+static const struct of_device_id clk_starfive_jh7110_match[] = {
{.compatible = "starfive,jh7110-clkgen"},
{ /* sentinel */ }
};
#include "clk-starfive-jh7110.h"
+/* external clocks */
+#define JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN (JH7110_CLK_ISP_END + 0)
+#define JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN (JH7110_CLK_ISP_END + 1)
+#define JH7110_ISP_TOP_CLK_BIST_APB_CLKGEN (JH7110_CLK_ISP_END + 2)
+#define JH7110_ISP_TOP_CLK_DVP_CLKGEN (JH7110_CLK_ISP_END + 3)
+
static const struct jh7110_clk_data jh7110_clk_isp_data[] __initconst = {
//syscon
JH7110__DIV(JH7110_DOM4_APB_FUNC, "dom4_apb_func",
clk_isp_noc_bus = devm_clk_get(priv->dev,
"u0_sft7110_noc_bus_clk_isp_axi");
- if (!IS_ERR(clk_isp_noc_bus)){
+ if (!IS_ERR(clk_isp_noc_bus)) {
ret = clk_prepare_enable(clk_isp_noc_bus);
- if(ret){
+ if (ret) {
dev_err(priv->dev, "clk_isp_noc_bus enable failed\n");
goto clk_noc_enable_failed;
}
- }else{
+ } else {
dev_err(priv->dev, "clk_isp_noc_bus get failed\n");
return PTR_ERR(clk_isp_noc_bus);
}
priv->dev, "rst_isp_noc_bus_n");
if (!IS_ERR(rst_isp_noc_bus)) {
ret = reset_control_deassert(rst_isp_noc_bus);
- if(ret){
+ if (ret) {
dev_err(priv->dev, "rst_isp_noc_bus deassert failed.\n");
goto rst_noc_deassert_failed;
}
- }else{
+ } else {
dev_err(priv->dev, "rst_isp_noc_bus get failed.\n");
ret = PTR_ERR(rst_isp_noc_bus);
goto rst_noc_get_failed;
clk_isp_2x = devm_clk_get(priv->dev,
"u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x");
- if (!IS_ERR(clk_isp_2x)){
+ if (!IS_ERR(clk_isp_2x)) {
ret = clk_prepare_enable(clk_isp_2x);
- if(ret){
+ if (ret) {
dev_err(priv->dev, "clk_isp_2x enable failed\n");
goto clk_2x_enable_failed;
}
- }else{
+ } else {
dev_err(priv->dev, "clk_isp_2x get failed\n");
ret = PTR_ERR(clk_isp_2x);
goto clk_2x_get_failed;
clk_isp_axi = devm_clk_get(priv->dev,
"u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi");
- if (!IS_ERR(clk_isp_axi)){
+ if (!IS_ERR(clk_isp_axi)) {
ret = clk_prepare_enable(clk_isp_axi);
- if(ret){
+ if (ret) {
dev_err(priv->dev, "clk_isp_axi enable failed\n");
goto clk_axi_enable_failed;
}
- }else{
+ } else {
dev_err(priv->dev, "clk_isp_axi get failed\n");
ret = PTR_ERR(clk_isp_axi);
goto clk_axi_get_failed;
priv->dev, "rst_isp_top_n");
if (!IS_ERR(rst_isp_n)) {
ret = reset_control_deassert(rst_isp_n);
- if(ret){
+ if (ret) {
dev_err(priv->dev, "rst_isp_n deassert failed.\n");
goto rst_n_deassert_failed;
}
- }else{
+ } else {
dev_err(priv->dev, "rst_isp_n get failed.\n");
ret = PTR_ERR(rst_isp_n);
goto rst_n_get_failed;
priv->dev, "rst_isp_top_axi");
if (!IS_ERR(rst_isp_axi)) {
ret = reset_control_deassert(rst_isp_axi);
- if(ret){
+ if (ret) {
dev_err(priv->dev, "rst_isp_axi deassert failed.\n");
goto rst_axi_deassert_failed;
}
- }else{
+ } else {
dev_err(priv->dev, "rst_isp_axi get failed.\n");
ret = PTR_ERR(rst_isp_axi);
goto rst_axi_get_failed;
.name = jh7110_clk_isp_data[idx].name,
.ops = starfive_jh7110_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH7110_CLK_MUX_MASK) \
- >> JH7110_CLK_MUX_SHIFT) + 1,
+ .num_parents = ((max & JH7110_CLK_MUX_MASK) >>
+ JH7110_CLK_MUX_SHIFT) + 1,
.flags = jh7110_clk_isp_data[idx].flags,
};
struct jh7110_clk *clk = &priv->reg[idx];
unsigned int i;
+ char *fw_name[4] = {
+ "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_bist_apb",
+ "u0_dom_isp_top_clk_dom_isp_top_clk_dvp"
+ };
for (i = 0; i < init.num_parents; i++) {
unsigned int pidx = jh7110_clk_isp_data[idx].parents[i];
else if (pidx < JH7110_CLK_ISP_END)
parents[i].hw = priv->pll[PLL_OFI(pidx)];
else if (pidx == JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN)
- parents[i].fw_name = \
- "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x";
+ parents[i].fw_name = fw_name[0];
else if (pidx == JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN)
- parents[i].fw_name = \
- "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi";
+ parents[i].fw_name = fw_name[1];
else if (pidx == JH7110_ISP_TOP_CLK_BIST_APB_CLKGEN)
- parents[i].fw_name = \
- "u0_dom_isp_top_clk_dom_isp_top_clk_bist_apb";
+ parents[i].fw_name = fw_name[2];
else if (pidx == JH7110_ISP_TOP_CLK_DVP_CLKGEN)
- parents[i].fw_name = \
- "u0_dom_isp_top_clk_dom_isp_top_clk_dvp";
+ parents[i].fw_name = fw_name[3];
}
clk->hw.init = &init;
devm_clk_put(priv->dev, clk_isp_2x);
devm_clk_put(priv->dev, clk_isp_noc_bus);
- dev_info(&pdev->dev,"starfive JH7110 clk_isp init successfully.");
+ dev_info(&pdev->dev, "starfive JH7110 clk_isp init successfully.");
return 0;
rst_axi_deassert_failed:
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 PLL Clock Generator Driver
+ *
+ * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/debugfs.h>
+#include <linux/init.h>
+
+#include "clk-starfive-jh7110-pll.h"
+
+static struct jh7110_clk_pll_data * __init
+ jh7110_pll_data_from(struct clk_hw *hw)
+{
+ return container_of(hw, struct jh7110_clk_pll_data, hw);
+}
+
+static unsigned long pll_calculate_freq(struct jh7110_clk_pll_data *data)
+{
+ u32 dacpd;
+ u32 dsmpd;
+ u32 fbdiv;
+ u32 prediv;
+ u32 postdiv1;
+ u32 frac;
+ unsigned long refclk;
+ u32 reg_value;
+ unsigned long frac_cal;
+ unsigned long freq;
+ struct pll_syscon_offset *offset = &data->offset;
+ struct pll_syscon_mask *mask = &data->mask;
+ struct pll_syscon_shift *shift = &data->shift;
+
+ if (regmap_read(data->sys_syscon_regmap,
+ offset->dacpd_offset, ®_value))
+ goto read_register_error;
+ dacpd = (reg_value & mask->dacpd_mask) >> shift->dacpd_shift;
+ dev_dbg(data->dev, "pll%d read register dacpd:%d\n", data->idx, dacpd);
+
+ if (regmap_read(data->sys_syscon_regmap,
+ offset->dsmpd_offset, ®_value))
+ goto read_register_error;
+ dsmpd = (reg_value & mask->dsmpd_mask) >> shift->dsmpd_shift;
+ dev_dbg(data->dev, "pll%d read register dsmpd:%d\n", data->idx, dsmpd);
+
+ if (regmap_read(data->sys_syscon_regmap,
+ offset->fbdiv_offset, ®_value))
+ goto read_register_error;
+ fbdiv = (reg_value & mask->fbdiv_mask) >> shift->fbdiv_shift;
+ /* fbdiv value should be 8 to 4095 */
+ if (fbdiv < 8)
+ goto read_register_error;
+ dev_dbg(data->dev, "pll%d read register fbdiv:%d\n", data->idx, fbdiv);
+
+ if (regmap_read(data->sys_syscon_regmap,
+ offset->prediv_offset, ®_value))
+ goto read_register_error;
+ prediv = (reg_value & mask->prediv_mask) >> shift->prediv_shift;
+ dev_dbg(data->dev, "pll%d read register prediv:%d\n", data->idx, prediv);
+
+ if (regmap_read(data->sys_syscon_regmap,
+ offset->postdiv1_offset, ®_value))
+ goto read_register_error;
+ /* postdiv1 = 2^reg */
+ postdiv1 = 1 << ((reg_value & mask->postdiv1_mask) >>
+ shift->postdiv1_shift);
+ dev_dbg(data->dev, "pll%d read register postdiv1:%d\n",
+ data->idx, postdiv1);
+
+ if (regmap_read(data->sys_syscon_regmap,
+ offset->frac_offset, ®_value))
+ goto read_register_error;
+ frac = (reg_value & mask->frac_mask) >> shift->frac_shift;
+ dev_dbg(data->dev, "pll%d read register frac:0x%x\n", data->idx, frac);
+
+ refclk = data->refclk_freq;
+ /* Integer Mode or Fraction Mode */
+ if ((dacpd == 1) && (dsmpd == 1))
+ frac_cal = 0;
+ else
+ frac_cal = (unsigned long) frac * FRAC_PATR_SIZE / (1 << 24);
+
+ freq = (unsigned long) refclk / FRAC_PATR_SIZE *
+ (fbdiv * FRAC_PATR_SIZE + frac_cal) / prediv / postdiv1;
+
+ dev_dbg(data->dev, "pll%d calculate freq:%ld\n", data->idx, freq);
+ return freq;
+
+read_register_error:
+ return 0;
+}
+
+static unsigned long pll_get_freq(struct jh7110_clk_pll_data *data)
+{
+ unsigned long freq;
+
+ freq = pll_calculate_freq(data);
+ if (freq == 0) {
+ dev_err(data->dev, "PLL calculate error or read syscon error.\n");
+ return 0;
+ }
+
+ return freq;
+}
+
+static int pll_select_freq_syscon(struct jh7110_clk_pll_data *data,
+ unsigned long target_rate)
+{
+ unsigned int id;
+ unsigned int pll_arry_size;
+ const struct starfive_pll_syscon_value *syscon_value;
+
+ if (data->idx == PLL0_INDEX)
+ pll_arry_size = ARRAY_SIZE(jh7110_pll0_syscon_freq);
+ else if (data->idx == PLL1_INDEX)
+ pll_arry_size = ARRAY_SIZE(jh7110_pll1_syscon_freq);
+ else
+ pll_arry_size = ARRAY_SIZE(jh7110_pll2_syscon_freq);
+
+ for (id = 0; id < pll_arry_size; id++) {
+ if (data->idx == PLL0_INDEX)
+ syscon_value = &jh7110_pll0_syscon_freq[id];
+ else if (data->idx == PLL1_INDEX)
+ syscon_value = &jh7110_pll1_syscon_freq[id];
+ else
+ syscon_value = &jh7110_pll2_syscon_freq[id];
+
+ if (target_rate == syscon_value->freq)
+ goto select_end;
+ }
+
+ dev_err(data->dev, "pll%d frequency:%ld do not match, please check it.\n",
+ data->idx, target_rate);
+ return -EINVAL;
+
+select_end:
+ data->freq_select_idx = id;
+ return 0;
+}
+
+static int pll_set_freq_syscon(struct jh7110_clk_pll_data *data)
+{
+ int ret;
+ const struct starfive_pll_syscon_value *syscon_value;
+ unsigned int freq_idx = data->freq_select_idx;
+ struct pll_syscon_offset *offset = &data->offset;
+ struct pll_syscon_mask *mask = &data->mask;
+ struct pll_syscon_shift *shift = &data->shift;
+
+ if (data->idx == PLL0_INDEX)
+ syscon_value = &jh7110_pll0_syscon_freq[freq_idx];
+ else if (data->idx == PLL1_INDEX)
+ syscon_value = &jh7110_pll1_syscon_freq[freq_idx];
+ else
+ syscon_value = &jh7110_pll2_syscon_freq[freq_idx];
+
+ dev_dbg(data->dev, "dacpd:offset=0x%x, mask=0x%x, shift=%d, value=%d\n",
+ offset->dacpd_offset, mask->dacpd_mask,
+ shift->dacpd_shift, syscon_value->dacpd);
+ ret = regmap_update_bits(data->sys_syscon_regmap, offset->dacpd_offset,
+ mask->dacpd_mask, (syscon_value->dacpd << shift->dacpd_shift));
+ if (ret)
+ goto set_failed;
+ dev_dbg(data->dev, "dsmpd:offset=%x, mask=%x, shift=%d, value=%d\n",
+ offset->dsmpd_offset, mask->dsmpd_mask,
+ shift->dsmpd_shift, syscon_value->dsmpd);
+ ret = regmap_update_bits(data->sys_syscon_regmap, offset->dsmpd_offset,
+ mask->dsmpd_mask, (syscon_value->dsmpd << shift->dsmpd_shift));
+ if (ret)
+ goto set_failed;
+
+ dev_dbg(data->dev, "prediv:offset=%x, mask=%x, shift=%d, value=%d\n",
+ offset->prediv_offset, mask->prediv_mask,
+ shift->prediv_shift, syscon_value->prediv);
+ ret = regmap_update_bits(data->sys_syscon_regmap, offset->prediv_offset,
+ mask->prediv_mask, (syscon_value->prediv << shift->prediv_shift));
+ if (ret)
+ goto set_failed;
+
+ dev_dbg(data->dev, "fbdiv:offset=%x, mask=%x, shift=%d, value=%d\n",
+ offset->fbdiv_offset, mask->fbdiv_mask,
+ shift->fbdiv_shift, syscon_value->fbdiv);
+ ret = regmap_update_bits(data->sys_syscon_regmap, offset->fbdiv_offset,
+ mask->fbdiv_mask, (syscon_value->fbdiv << shift->fbdiv_shift));
+ if (ret)
+ goto set_failed;
+
+ dev_dbg(data->dev, "postdiv:offset=0x%x, mask=0x%x, shift=%d, value=%d\n",
+ offset->postdiv1_offset, mask->postdiv1_mask,
+ shift->postdiv1_shift, syscon_value->postdiv1);
+ ret = regmap_update_bits(data->sys_syscon_regmap,
+ offset->postdiv1_offset, mask->postdiv1_mask,
+ ((syscon_value->postdiv1 >> 1) << shift->postdiv1_shift));
+ if (ret)
+ goto set_failed;
+ /* frac */
+ if ((syscon_value->dacpd == 0) && (syscon_value->dsmpd == 0)) {
+ dev_dbg(data->dev, "frac:offset=0x%x mask=0x%x shift=%d value=0x%x\n",
+ offset->frac_offset, mask->frac_mask,
+ shift->frac_shift, syscon_value->frac);
+ ret = regmap_update_bits(data->sys_syscon_regmap, offset->frac_offset,
+ mask->frac_mask, (syscon_value->frac << shift->frac_shift));
+ if (ret)
+ goto set_failed;
+ }
+
+ dev_dbg(data->dev, "pll%d set syscon register done and rate is %ld\n",
+ data->idx, syscon_value->freq);
+ return 0;
+
+set_failed:
+ dev_err(data->dev, "pll set syscon failed:%d\n", ret);
+ return ret;
+}
+
+static unsigned long jh7110_clk_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
+
+ return pll_get_freq(data);
+}
+
+static int jh7110_clk_pll_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ int ret;
+ struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
+
+ ret = pll_select_freq_syscon(data, req->rate);
+ if (ret)
+ return ret;
+
+ if (data->idx == PLL0_INDEX)
+ req->rate = jh7110_pll0_syscon_freq[data->freq_select_idx].freq;
+ else if (data->idx == PLL1_INDEX)
+ req->rate = jh7110_pll1_syscon_freq[data->freq_select_idx].freq;
+ else
+ req->rate = jh7110_pll2_syscon_freq[data->freq_select_idx].freq;
+
+ return 0;
+}
+
+static int jh7110_clk_pll_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
+
+ return pll_set_freq_syscon(data);
+
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void jh7110_clk_pll_debug_init(struct clk_hw *hw,
+ struct dentry *dentry)
+{
+ static const struct debugfs_reg32 jh7110_clk_pll_reg = {
+ .name = "CTRL",
+ .offset = 0,
+ };
+ struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
+ struct debugfs_regset32 *regset;
+
+ regset = devm_kzalloc(data->dev, sizeof(*regset), GFP_KERNEL);
+ if (!regset)
+ return;
+
+ regset->regs = &jh7110_clk_pll_reg;
+ regset->nregs = 1;
+
+ debugfs_create_regset32("registers", 0400, dentry, regset);
+}
+#else
+#define jh7110_clk_debug_init NULL
+#endif
+
+static const struct clk_ops jh7110_clk_pll_ops = {
+ .recalc_rate = jh7110_clk_pll_recalc_rate,
+ .determine_rate = jh7110_clk_pll_determine_rate,
+ .set_rate = jh7110_clk_pll_set_rate,
+ .debug_init = jh7110_clk_pll_debug_init,
+};
+
+static int pll_data_offset_get(struct jh7110_clk_pll_data *data,
+ struct of_phandle_args *args, int index)
+{
+ struct pll_syscon_offset *offset = &data->offset;
+ struct pll_syscon_mask *mask = &data->mask;
+ struct pll_syscon_shift *shift = &data->shift;
+
+ if (index == PLL0_INDEX) {
+ offset->dacpd_offset = args->args[0];
+ offset->dsmpd_offset = args->args[0];
+ offset->fbdiv_offset = args->args[1];
+ offset->frac_offset = args->args[2];
+ offset->prediv_offset = args->args[3];
+ offset->postdiv1_offset = args->args[2];
+
+ mask->dacpd_mask = PLL0_DACPD_MASK;
+ mask->dsmpd_mask = PLL0_DSMPD_MASK;
+ mask->fbdiv_mask = PLL0_FBDIV_MASK;
+ mask->frac_mask = PLL0_FRAC_MASK;
+ mask->prediv_mask = PLL0_PREDIV_MASK;
+ mask->postdiv1_mask = PLL0_POSTDIV1_MASK;
+
+ shift->dacpd_shift = PLL0_DACPD_SHIFT;
+ shift->dsmpd_shift = PLL0_DSMPD_SHIFT;
+ shift->fbdiv_shift = PLL0_FBDIV_SHIFT;
+ shift->frac_shift = PLL0_FRAC_SHIFT;
+ shift->prediv_shift = PLL0_PREDIV_SHIFT;
+ shift->postdiv1_shift = PLL0_POSTDIV1_SHIFT;
+ } else if (index == PLL1_INDEX) {
+ offset->dacpd_offset = args->args[3];
+ offset->dsmpd_offset = args->args[3];
+ offset->fbdiv_offset = args->args[3];
+ offset->frac_offset = args->args[4];
+ offset->prediv_offset = args->args[5];
+ offset->postdiv1_offset = args->args[4];
+
+ mask->dacpd_mask = PLL1_DACPD_MASK;
+ mask->dsmpd_mask = PLL1_DSMPD_MASK;
+ mask->fbdiv_mask = PLL1_FBDIV_MASK;
+ mask->frac_mask = PLL1_FRAC_MASK;
+ mask->prediv_mask = PLL1_PREDIV_MASK;
+ mask->postdiv1_mask = PLL1_POSTDIV1_MASK;
+
+ shift->dacpd_shift = PLL1_DACPD_SHIFT;
+ shift->dsmpd_shift = PLL1_DSMPD_SHIFT;
+ shift->fbdiv_shift = PLL1_FBDIV_SHIFT;
+ shift->frac_shift = PLL1_FRAC_SHIFT;
+ shift->prediv_shift = PLL1_PREDIV_SHIFT;
+ shift->postdiv1_shift = PLL1_POSTDIV1_SHIFT;
+ } else if (index == PLL2_INDEX) {
+ offset->dacpd_offset = args->args[5];
+ offset->dsmpd_offset = args->args[5];
+ offset->fbdiv_offset = args->args[5];
+ offset->frac_offset = args->args[6];
+ offset->prediv_offset = args->args[7];
+ offset->postdiv1_offset = args->args[6];
+
+ mask->dacpd_mask = PLL2_DACPD_MASK;
+ mask->dsmpd_mask = PLL2_DSMPD_MASK;
+ mask->fbdiv_mask = PLL2_FBDIV_MASK;
+ mask->frac_mask = PLL2_FRAC_MASK;
+ mask->prediv_mask = PLL2_PREDIV_MASK;
+ mask->postdiv1_mask = PLL2_POSTDIV1_MASK;
+
+ shift->dacpd_shift = PLL2_DACPD_SHIFT;
+ shift->dsmpd_shift = PLL2_DSMPD_SHIFT;
+ shift->fbdiv_shift = PLL2_FBDIV_SHIFT;
+ shift->frac_shift = PLL2_FRAC_SHIFT;
+ shift->prediv_shift = PLL2_PREDIV_SHIFT;
+ shift->postdiv1_shift = PLL2_POSTDIV1_SHIFT;
+ } else
+ return -ENOENT;
+
+ return 0;
+}
+
+int __init clk_starfive_jh7110_pll_init(struct platform_device *pdev,
+ struct jh7110_clk_pll_data *pll_priv)
+{
+ int ret;
+ struct of_phandle_args args;
+ struct regmap *pll_syscon_regmap;
+ unsigned int idx;
+ struct clk *osc_clk;
+ unsigned long refclk_freq;
+ struct jh7110_clk_pll_data *data;
+ char *pll_name[3] = {
+ "pll0_out",
+ "pll1_out",
+ "pll2_out"
+ };
+
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "starfive,sys-syscon", 8, 0, &args);
+ if (ret) {
+ dev_warn(&pdev->dev, "Failed to parse starfive,sys-syscon\n");
+ goto pll_init_failed;
+ }
+
+ pll_syscon_regmap = syscon_node_to_regmap(args.np);
+ of_node_put(args.np);
+ if (IS_ERR(pll_syscon_regmap)) {
+ ret = PTR_ERR(pll_syscon_regmap);
+ goto pll_init_failed;
+ }
+
+ osc_clk = clk_get(&pdev->dev, "osc");
+ if (!IS_ERR(osc_clk)) {
+ refclk_freq = clk_get_rate(osc_clk);
+ clk_put(osc_clk);
+ } else {
+ ret = PTR_ERR(osc_clk);
+ dev_err(&pdev->dev, "get osc clk failed :%d.\n", ret);
+ goto pll_init_failed;
+ }
+
+ for (idx = 0; idx < PLL_INDEX_MAX; idx++) {
+ struct clk_parent_data parents = {
+ .fw_name = "osc",
+ };
+ struct clk_init_data init = {
+ .name = pll_name[idx],
+ .ops = &jh7110_clk_pll_ops,
+ .parent_data = &parents,
+ .num_parents = 1,
+ .flags = 0,
+ };
+
+ /* pll1 use default freq and does not be changed */
+ if (idx == PLL1_INDEX)
+ continue;
+
+ data = &pll_priv[idx];
+ data->dev = &pdev->dev;
+ data->sys_syscon_regmap = pll_syscon_regmap;
+
+ ret = pll_data_offset_get(data, &args, idx);
+ if (ret)
+ goto pll_init_failed;
+
+ data->hw.init = &init;
+ data->idx = idx;
+ data->refclk_freq = refclk_freq;
+
+ ret = devm_clk_hw_register(&pdev->dev, &data->hw);
+ if (ret)
+ return ret;
+ }
+
+ dev_info(&pdev->dev, "PLL0 and PLL2 clock be set done\n");
+
+/* Change PLL2 rate before other driver up */
+ if (PLL2_DEFAULT_FREQ) {
+ struct clk *pll2_clk = pll_priv[PLL2_INDEX].hw.clk;
+
+ if (clk_set_rate(pll2_clk, PLL2_DEFAULT_FREQ))
+ dev_info(&pdev->dev, "set pll2 failed\n");
+ }
+
+ return 0;
+
+pll_init_failed:
+ return ret;
+}
+
+
+
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * StarFive JH7110 PLL Clock Generator Driver
+ *
+ * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
+ */
+
+#ifndef _CLK_STARFIVE_JH7110_PLL_H_
+#define _CLK_STARFIVE_JH7110_PLL_H_
+
+/*
+ * If set PLL2_DEFAULT_FREQ NULL of 0 , then PLL2 frequency is original.
+ * If set PLL2_DEFAULT_FREQ one of 'starfive_pll2_freq_value', then PLL2
+ * frequency will be set the new rate during clock tree registering.
+ */
+#define PLL2_DEFAULT_FREQ PLL2_FREQ_12288_VALUE
+
+#define PLL0_INDEX 0
+#define PLL1_INDEX 1
+#define PLL2_INDEX 2
+
+#define PLL_INDEX_MAX 3
+
+#define PLL0_DACPD_SHIFT 24
+#define PLL0_DACPD_MASK 0x1000000
+#define PLL0_DSMPD_SHIFT 25
+#define PLL0_DSMPD_MASK 0x2000000
+#define PLL0_FBDIV_SHIFT 0
+#define PLL0_FBDIV_MASK 0xFFF
+#define PLL0_FRAC_SHIFT 0
+#define PLL0_FRAC_MASK 0xFFFFFF
+#define PLL0_POSTDIV1_SHIFT 28
+#define PLL0_POSTDIV1_MASK 0x30000000
+#define PLL0_PREDIV_SHIFT 0
+#define PLL0_PREDIV_MASK 0x3F
+
+#define PLL1_DACPD_SHIFT 15
+#define PLL1_DACPD_MASK 0x8000
+#define PLL1_DSMPD_SHIFT 16
+#define PLL1_DSMPD_MASK 0x10000
+#define PLL1_FBDIV_SHIFT 17
+#define PLL1_FBDIV_MASK 0x1FFE0000
+#define PLL1_FRAC_SHIFT 0
+#define PLL1_FRAC_MASK 0xFFFFFF
+#define PLL1_POSTDIV1_SHIFT 28
+#define PLL1_POSTDIV1_MASK 0x30000000
+#define PLL1_PREDIV_SHIFT 0
+#define PLL1_PREDIV_MASK 0x3F
+
+#define PLL2_DACPD_SHIFT 15
+#define PLL2_DACPD_MASK 0x8000
+#define PLL2_DSMPD_SHIFT 16
+#define PLL2_DSMPD_MASK 0x10000
+#define PLL2_FBDIV_SHIFT 17
+#define PLL2_FBDIV_MASK 0x1FFE0000
+#define PLL2_FRAC_SHIFT 0
+#define PLL2_FRAC_MASK 0xFFFFFF
+#define PLL2_POSTDIV1_SHIFT 28
+#define PLL2_POSTDIV1_MASK 0x30000000
+#define PLL2_PREDIV_SHIFT 0
+#define PLL2_PREDIV_MASK 0x3F
+
+#define FRAC_PATR_SIZE 1000
+
+struct pll_syscon_offset {
+ u32 dacpd_offset;
+ u32 dsmpd_offset;
+ u32 fbdiv_offset;
+ u32 frac_offset;
+ u32 prediv_offset;
+ u32 postdiv1_offset;
+};
+
+struct pll_syscon_mask {
+ u32 dacpd_mask;
+ u32 dsmpd_mask;
+ u32 fbdiv_mask;
+ u32 frac_mask;
+ u32 prediv_mask;
+ u32 postdiv1_mask;
+};
+
+struct pll_syscon_shift {
+ u32 dacpd_shift;
+ u32 dsmpd_shift;
+ u32 fbdiv_shift;
+ u32 frac_shift;
+ u32 prediv_shift;
+ u32 postdiv1_shift;
+};
+
+struct jh7110_clk_pll_data {
+ struct device *dev;
+ struct clk_hw hw;
+ unsigned long refclk_freq;
+ unsigned int idx;
+ unsigned int freq_select_idx;
+
+ struct regmap *sys_syscon_regmap;
+ struct pll_syscon_offset offset;
+ struct pll_syscon_mask mask;
+ struct pll_syscon_shift shift;
+};
+
+struct starfive_pll_syscon_value {
+ unsigned long freq;
+ u32 prediv;
+ u32 fbdiv;
+ u32 postdiv1;
+/* Both daxpd and dsmpd set 1 while integer multiple mode */
+/* Both daxpd and dsmpd set 0 while fraction multiple mode */
+ u32 dacpd;
+ u32 dsmpd;
+/* frac value should be decimals multiplied by 2^24 */
+ u32 frac;
+};
+
+enum starfive_pll0_freq_value {
+ PLL0_FREQ_375_VALUE = 375000000,
+ PLL0_FREQ_500_VALUE = 500000000,
+ PLL0_FREQ_625_VALUE = 625000000,
+ PLL0_FREQ_750_VALUE = 750000000,
+ PLL0_FREQ_875_VALUE = 875000000,
+ PLL0_FREQ_1000_VALUE = 1000000000,
+ PLL0_FREQ_1250_VALUE = 1250000000,
+ PLL0_FREQ_1375_VALUE = 1375000000,
+ PLL0_FREQ_1500_VALUE = 1500000000,
+ PLL0_FREQ_1625_VALUE = 1625000000,
+ PLL0_FREQ_1750_VALUE = 1750000000
+};
+
+enum starfive_pll0_freq {
+ PLL0_FREQ_375 = 0,
+ PLL0_FREQ_500,
+ PLL0_FREQ_625,
+ PLL0_FREQ_750,
+ PLL0_FREQ_875,
+ PLL0_FREQ_1000,
+ PLL0_FREQ_1250,
+ PLL0_FREQ_1375,
+ PLL0_FREQ_1500,
+ PLL0_FREQ_1625,
+ PLL0_FREQ_1750,
+ PLL0_FREQ_MAX
+};
+
+enum starfive_pll1_freq_value {
+ PLL1_FREQ_1066_VALUE = 1066000000,
+};
+
+enum starfive_pll1_freq {
+ PLL1_FREQ_1066 = 0,
+};
+
+enum starfive_pll2_freq_value {
+ PLL2_FREQ_1188_VALUE = 1188000000,
+ PLL2_FREQ_12288_VALUE = 1228800000,
+};
+
+enum starfive_pll2_freq {
+ PLL2_FREQ_1188 = 0,
+ PLL2_FREQ_12288,
+};
+
+static const struct starfive_pll_syscon_value
+ jh7110_pll0_syscon_freq[PLL0_FREQ_MAX] = {
+ [PLL0_FREQ_375] = {
+ .freq = PLL0_FREQ_375_VALUE,
+ .prediv = 8,
+ .fbdiv = 125,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL0_FREQ_500] = {
+ .freq = PLL0_FREQ_500_VALUE,
+ .prediv = 6,
+ .fbdiv = 125,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL0_FREQ_625] = {
+ .freq = PLL0_FREQ_625_VALUE,
+ .prediv = 24,
+ .fbdiv = 625,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL0_FREQ_750] = {
+ .freq = PLL0_FREQ_750_VALUE,
+ .prediv = 4,
+ .fbdiv = 125,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL0_FREQ_875] = {
+ .freq = PLL0_FREQ_875_VALUE,
+ .prediv = 24,
+ .fbdiv = 875,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL0_FREQ_1000] = {
+ .freq = PLL0_FREQ_1000_VALUE,
+ .prediv = 3,
+ .fbdiv = 125,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL0_FREQ_1250] = {
+ .freq = PLL0_FREQ_1250_VALUE,
+ .prediv = 12,
+ .fbdiv = 625,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL0_FREQ_1375] = {
+ .freq = PLL0_FREQ_1375_VALUE,
+ .prediv = 24,
+ .fbdiv = 1375,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL0_FREQ_1500] = {
+ .freq = PLL0_FREQ_1500_VALUE,
+ .prediv = 2,
+ .fbdiv = 125,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL0_FREQ_1625] = {
+ .freq = PLL0_FREQ_1625_VALUE,
+ .prediv = 24,
+ .fbdiv = 1625,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL0_FREQ_1750] = {
+ .freq = PLL0_FREQ_1750_VALUE,
+ .prediv = 12,
+ .fbdiv = 875,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+};
+
+static const struct starfive_pll_syscon_value
+ jh7110_pll1_syscon_freq[] = {
+ [PLL1_FREQ_1066] = {
+ .freq = PLL1_FREQ_1066_VALUE,
+ .prediv = 12,
+ .fbdiv = 533,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+};
+
+static const struct starfive_pll_syscon_value
+ jh7110_pll2_syscon_freq[] = {
+ [PLL2_FREQ_1188] = {
+ .freq = PLL2_FREQ_1188_VALUE,
+ .prediv = 2,
+ .fbdiv = 99,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+ [PLL2_FREQ_12288] = {
+ .freq = PLL2_FREQ_12288_VALUE,
+ .prediv = 5,
+ .fbdiv = 256,
+ .postdiv1 = 1,
+ .dacpd = 1,
+ .dsmpd = 1,
+ },
+};
+
+int __init clk_starfive_jh7110_pll_init(struct platform_device *pdev,
+ struct jh7110_clk_pll_data *pll_priv);
+
+#endif
#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
#include "clk-starfive-jh7110.h"
+/* external clocks */
+#define JH7110_OSC (JH7110_CLK_END + 0)
+/* stg external clocks */
+#define JH7110_STG_APB (JH7110_CLK_END + 11)
+
static const struct jh7110_clk_data jh7110_clk_stg_data[] __initconst = {
//hifi4
JH7110_GATE(JH7110_HIFI4_CLK_CORE, "u0_hifi4_clk_core",
.name = jh7110_clk_stg_data[idx].name,
.ops = starfive_jh7110_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH7110_CLK_MUX_MASK) \
- >> JH7110_CLK_MUX_SHIFT) + 1,
+ .num_parents = ((max & JH7110_CLK_MUX_MASK) >>
+ JH7110_CLK_MUX_SHIFT) + 1,
.flags = jh7110_clk_stg_data[idx].flags,
};
struct jh7110_clk *clk = &priv->reg[idx];
if (pidx < JH7110_CLK_STG_REG_END)
parents[i].hw = &priv->reg[pidx].hw;
- else if ((pidx < JH7110_CLK_STG_END) && \
+ else if ((pidx < JH7110_CLK_STG_END) &&
(pidx > JH7110_CLK_SYS_END))
parents[i].hw = priv->pll[PLL_OF(pidx)];
+ else if (pidx == JH7110_OSC)
+ parents[i].fw_name = "osc";
else if (pidx == JH7110_STG_APB)
parents[i].fw_name = "stg_apb";
}
return ret;
}
- dev_dbg(&pdev->dev,"starfive JH7110 clk_stg init successfully.");
+ dev_dbg(&pdev->dev, "starfive JH7110 clk_stg init successfully.");
return 0;
}
#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
#include "clk-starfive-jh7110.h"
+/* sys external clocks */
+#define JH7110_OSC (JH7110_CLK_END + 0)
+#define JH7110_GMAC1_RMII_REFIN (JH7110_CLK_END + 1)
+#define JH7110_GMAC1_RGMII_RXIN (JH7110_CLK_END + 2)
+#define JH7110_I2STX_BCLK_EXT (JH7110_CLK_END + 3)
+#define JH7110_I2STX_LRCK_EXT (JH7110_CLK_END + 4)
+#define JH7110_I2SRX_BCLK_EXT (JH7110_CLK_END + 5)
+#define JH7110_I2SRX_LRCK_EXT (JH7110_CLK_END + 6)
+#define JH7110_TDM_EXT (JH7110_CLK_END + 7)
+#define JH7110_MCLK_EXT (JH7110_CLK_END + 8)
+#define JH7110_JTAG_TCK_INNER (JH7110_CLK_END + 9)
+#define JH7110_BIST_APB (JH7110_CLK_END + 10)
+
static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
/*root*/
JH7110__MUX(JH7110_CPU_ROOT, "cpu_root", PARENT_NUMS_2,
priv->sys_base = devm_platform_ioremap_resource_byname(pdev, "sys");
if (IS_ERR(priv->sys_base))
return PTR_ERR(priv->sys_base);
-
+
+#ifndef CONFIG_CLK_STARFIVE_JH7110_PLL
priv->pll[PLL_OF(JH7110_PLL0_OUT)] =
clk_hw_register_fixed_rate(priv->dev,
"pll0_out", "osc", 0, 1250000000);
if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL0_OUT)]))
return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL0_OUT)]);
+#endif
priv->pll[PLL_OF(JH7110_PLL1_OUT)] =
clk_hw_register_fixed_rate(priv->dev,
if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]))
return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]);
+#ifndef CONFIG_CLK_STARFIVE_JH7110_PLL
priv->pll[PLL_OF(JH7110_PLL2_OUT)] =
clk_hw_register_fixed_rate(priv->dev,
"pll2_out", "osc", 0, 1228800000);
if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL2_OUT)]))
return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL2_OUT)]);
+#endif
priv->pll[PLL_OF(JH7110_AON_APB)] =
devm_clk_hw_register_fixed_factor(priv->dev,
.name = jh7110_clk_sys_data[idx].name,
.ops = starfive_jh7110_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH7110_CLK_MUX_MASK) \
- >> JH7110_CLK_MUX_SHIFT) + 1,
+ .num_parents = ((max & JH7110_CLK_MUX_MASK) >>
+ JH7110_CLK_MUX_SHIFT) + 1,
.flags = jh7110_clk_sys_data[idx].flags,
};
struct jh7110_clk *clk = &priv->reg[idx];
if (pidx < JH7110_CLK_SYS_REG_END)
parents[i].hw = &priv->reg[pidx].hw;
- else if ((pidx < JH7110_CLK_SYS_END) && \
+#ifdef CONFIG_CLK_STARFIVE_JH7110_PLL
+ else if ((pidx == JH7110_PLL0_OUT) || (pidx == JH7110_PLL2_OUT))
+ parents[i].hw = &priv->pll_priv[PLL_OF(pidx)].hw;
+#endif
+ else if ((pidx < JH7110_CLK_SYS_END) &&
(pidx > JH7110_CLK_SYS_REG_END))
parents[i].hw = priv->pll[PLL_OF(pidx)];
else if (pidx == JH7110_OSC)
return ret;
}
- dev_dbg(&pdev->dev,"starfive JH7110 clk_sys init successfully.");
+ dev_dbg(&pdev->dev, "starfive JH7110 clk_sys init successfully.");
return 0;
}
#include <dt-bindings/clock/starfive-jh7110-vout.h>
#include "clk-starfive-jh7110.h"
+/* external clocks */
+#define JH7110_HDMITX0_PIXELCLK (JH7110_CLK_VOUT_END + 0)
+#define JH7110_MIPITX_DPHY_RXESC (JH7110_CLK_VOUT_END + 1)
+#define JH7110_MIPITX_DPHY_TXBYTEHS (JH7110_CLK_VOUT_END + 2)
+
static const struct jh7110_clk_data jh7110_clk_vout_data[] __initconst = {
//divider
JH7110__DIV(JH7110_APB, "apb", 8, JH7110_DISP_AHB),
GATE_FLAG_NORMAL, PARENT_NUMS_2,
JH7110_DC8200_PIX0,
JH7110_HDMITX0_PIXELCLK),
-
+
JH7110_GMUX(JH7110_DOM_VOUT_TOP_LCD_CLK, "dom_vout_top_lcd_clk",
GATE_FLAG_NORMAL, PARENT_NUMS_2,
JH7110_U0_DC8200_CLK_PIX0_OUT,
}
clk_vout_src = devm_clk_get(priv->dev, "vout_src");
- if (!IS_ERR(clk_vout_src)){
+ if (!IS_ERR(clk_vout_src)) {
ret = clk_prepare_enable(clk_vout_src);
- if(ret){
+ if (ret) {
dev_err(priv->dev, "clk_vout_src enable failed\n");
goto clk_src_enable_failed;
}
- }else{
+ } else {
dev_err(priv->dev, "clk_vout_src get failed\n");
return PTR_ERR(clk_vout_src);
}
priv->dev, "vout_src");
if (!IS_ERR(rst_vout_src)) {
ret = reset_control_deassert(rst_vout_src);
- if(ret){
+ if (ret) {
dev_err(priv->dev, "rst_vout_src deassert failed.\n");
goto rst_src_deassert_failed;
}
- }else{
+ } else {
dev_err(priv->dev, "rst_vout_src get failed.\n");
ret = PTR_ERR(rst_vout_src);
goto rst_src_get_failed;
}
clk_vout_top_ahb = devm_clk_get(priv->dev, "vout_top_ahb");
- if (!IS_ERR(clk_vout_top_ahb)){
+ if (!IS_ERR(clk_vout_top_ahb)) {
ret = clk_prepare_enable(clk_vout_top_ahb);
- if(ret){
+ if (ret) {
dev_err(priv->dev, "clk_vout_top_ahb enable failed\n");
goto clk_ahb_enable_failed;
}
- }else{
+ } else {
dev_err(priv->dev, "clk_vout_top_ahb get failed\n");
ret = PTR_ERR(clk_vout_top_ahb);
goto clk_ahb_get_failed;
priv->dev, "hdmitx0_sck",
"u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_bclk",
0, 1, 1);
-
+
priv->pll[PLL_OFV(JH7110_MIPI_DPHY_REF)] =
devm_clk_hw_register_fixed_factor(
priv->dev, "mipi_dphy_ref",
priv->pll[PLL_OFV(JH7110_HDMI_TX_CLK_REF)] =
devm_clk_hw_register_fixed_factor(priv->dev,
"u0_hdmi_tx_clk_ref", "hdmi_phy_ref", 0, 1, 1);
-
+
priv->pll[PLL_OFV(JH7110_U0_DC8200_CLK_PIX0_OUT)] =
devm_clk_hw_register_fixed_factor(priv->dev,
"u0_dc8200_clk_pix0_out",
.name = jh7110_clk_vout_data[idx].name,
.ops = starfive_jh7110_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH7110_CLK_MUX_MASK) \
- >> JH7110_CLK_MUX_SHIFT) + 1,
+ .num_parents = ((max & JH7110_CLK_MUX_MASK) >>
+ JH7110_CLK_MUX_SHIFT) + 1,
.flags = jh7110_clk_vout_data[idx].flags,
};
struct jh7110_clk *clk = &priv->reg[idx];
if (pidx < JH7110_DISP_ROOT)
parents[i].hw = &priv->reg[pidx].hw;
else if (pidx < JH7110_CLK_VOUT_END)
- parents[i].hw = \
- priv->pll[PLL_OFV(pidx)];
+ parents[i].hw = priv->pll[PLL_OFV(pidx)];
else if (pidx == JH7110_HDMITX0_PIXELCLK)
parents[i].fw_name = "hdmitx0_pixelclk";
else if (pidx == JH7110_MIPITX_DPHY_RXESC)
reset_control_put(rst_vout_src);
devm_clk_put(priv->dev, clk_vout_top_ahb);
- dev_info(&pdev->dev,"starfive JH7110 clk_vout init successfully.");
+ dev_info(&pdev->dev, "starfive JH7110 clk_vout init successfully.");
return 0;
clk_ahb_enable_failed:
}
-static const struct of_device_id clk_starfive_jh7110_vout_match[] = {
+static const struct of_device_id clk_starfive_jh7110_vout_match[] = {
{.compatible = "starfive,jh7110-clk-vout" },
{ /* sentinel */ }
};
-// SPDX-License-Identifier: GPL-2.0
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* StarFive JH7110 Clock Generator Driver
*
#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
#include <dt-bindings/clock/starfive-jh7110-vout.h>
#include <dt-bindings/clock/starfive-jh7110-isp.h>
+#include "clk-starfive-jh7110-pll.h"
/* register flags */
#define JH7110_CLK_SYS_FLAG 1
void __iomem *vout_base;
void __iomem *isp_base;
struct clk_hw *pll[PLL_OF(JH7110_CLK_END)];
+#ifdef CONFIG_CLK_STARFIVE_JH7110_PLL
+ struct jh7110_clk_pll_data pll_priv[PLL_INDEX_MAX];
+#endif
struct jh7110_clk reg[];
};
-#define JH7110_GATE(_idx, _name, _flags, _parent) [_idx] = { \
- .name = _name, \
- .flags = CLK_SET_RATE_PARENT | (_flags), \
- .max = JH7110_CLK_ENABLE, \
- .parents = { [0] = _parent }, \
+#define JH7110_GATE(_idx, _name, _flags, _parent)\
+[_idx] = {\
+ .name = _name,\
+ .flags = CLK_SET_RATE_PARENT | (_flags),\
+ .max = JH7110_CLK_ENABLE,\
+ .parents = { [0] = _parent },\
}
-#define JH7110__DIV(_idx, _name, _max, _parent) [_idx] = { \
- .name = _name, \
- .flags = 0, \
- .max = _max, \
- .parents = { [0] = _parent }, \
+#define JH7110__DIV(_idx, _name, _max, _parent)\
+[_idx] = {\
+ .name = _name,\
+ .flags = 0,\
+ .max = _max,\
+ .parents = { [0] = _parent },\
}
-#define JH7110_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
- .name = _name, \
- .flags = _flags, \
- .max = JH7110_CLK_ENABLE | (_max), \
- .parents = { [0] = _parent }, \
+#define JH7110_GDIV(_idx, _name, _flags, _max, _parent)\
+[_idx] = {\
+ .name = _name,\
+ .flags = _flags,\
+ .max = JH7110_CLK_ENABLE | (_max),\
+ .parents = { [0] = _parent },\
}
-#define JH7110__MUX(_idx, _name, _nparents, ...) [_idx] = { \
- .name = _name, \
- .flags = 0, \
- .max = ((_nparents) - 1) << JH7110_CLK_MUX_SHIFT, \
- .parents = { __VA_ARGS__ }, \
+#define JH7110__MUX(_idx, _name, _nparents, ...)\
+[_idx] = {\
+ .name = _name,\
+ .flags = 0,\
+ .max = ((_nparents) - 1) << JH7110_CLK_MUX_SHIFT,\
+ .parents = { __VA_ARGS__ },\
}
-#define JH7110_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
- .name = _name, \
- .flags = _flags, \
- .max = JH7110_CLK_ENABLE | \
- (((_nparents) - 1) << JH7110_CLK_MUX_SHIFT), \
- .parents = { __VA_ARGS__ }, \
+#define JH7110_GMUX(_idx, _name, _flags, _nparents, ...)\
+[_idx] = {\
+ .name = _name,\
+ .flags = _flags,\
+ .max = JH7110_CLK_ENABLE | \
+ (((_nparents) - 1) << JH7110_CLK_MUX_SHIFT),\
+ .parents = { __VA_ARGS__ },\
}
-#define JH7110_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
- .name = _name, \
- .flags = 0, \
- .max = (((_nparents) - 1) << JH7110_CLK_MUX_SHIFT) | (_max), \
- .parents = { __VA_ARGS__ }, \
+#define JH7110_MDIV(_idx, _name, _max, _nparents, ...)\
+[_idx] = {\
+ .name = _name,\
+ .flags = 0,\
+ .max = (((_nparents) - 1) << JH7110_CLK_MUX_SHIFT) | (_max),\
+ .parents = { __VA_ARGS__ },\
}
-#define JH7110__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
- .name = _name, \
- .flags = _flags, \
- .max = JH7110_CLK_ENABLE | \
- (((_nparents) - 1) << JH7110_CLK_MUX_SHIFT) | (_max), \
- .parents = { __VA_ARGS__ }, \
+#define JH7110__GMD(_idx, _name, _flags, _max, _nparents, ...)\
+[_idx] = {\
+ .name = _name,\
+ .flags = _flags,\
+ .max = JH7110_CLK_ENABLE | \
+ (((_nparents) - 1) << JH7110_CLK_MUX_SHIFT) | (_max),\
+ .parents = { __VA_ARGS__ },\
}
-#define JH7110__INV(_idx, _name, _parent) [_idx] = { \
- .name = _name, \
- .flags = CLK_SET_RATE_PARENT, \
- .max = JH7110_CLK_INVERT, \
- .parents = { [0] = _parent }, \
+#define JH7110__INV(_idx, _name, _parent)\
+[_idx] = {\
+ .name = _name,\
+ .flags = CLK_SET_RATE_PARENT,\
+ .max = JH7110_CLK_INVERT,\
+ .parents = { [0] = _parent },\
}
void __iomem *jh7110_clk_reg_addr_get(struct jh7110_clk *clk);
const struct clk_ops *starfive_jh7110_clk_ops(u32 max);
-int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev, \
+int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev,
struct jh7110_clk_priv *priv);
-int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev, \
+int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev,
struct jh7110_clk_priv *priv);
-int __init clk_starfive_jh7110_aon_init(struct platform_device *pdev, \
+int __init clk_starfive_jh7110_aon_init(struct platform_device *pdev,
struct jh7110_clk_priv *priv);
#endif
#define JH7110_CLK_END 339
-/* sys external clocks */
-#define JH7110_OSC (JH7110_CLK_END + 0)
-#define JH7110_GMAC1_RMII_REFIN (JH7110_CLK_END + 1)
-#define JH7110_GMAC1_RGMII_RXIN (JH7110_CLK_END + 2)
-#define JH7110_I2STX_BCLK_EXT (JH7110_CLK_END + 3)
-#define JH7110_I2STX_LRCK_EXT (JH7110_CLK_END + 4)
-#define JH7110_I2SRX_BCLK_EXT (JH7110_CLK_END + 5)
-#define JH7110_I2SRX_LRCK_EXT (JH7110_CLK_END + 6)
-#define JH7110_TDM_EXT (JH7110_CLK_END + 7)
-#define JH7110_MCLK_EXT (JH7110_CLK_END + 8)
-#define JH7110_JTAG_TCK_INNER (JH7110_CLK_END + 9)
-#define JH7110_BIST_APB (JH7110_CLK_END + 10)
-
-/* stg external clocks */
-#define JH7110_STG_APB (JH7110_CLK_END + 11)
-
-/* aon external clocks */
-#define JH7110_GMAC0_RMII_REFIN (JH7110_CLK_END + 12)
-#define JH7110_GMAC0_RGMII_RXIN (JH7110_CLK_END + 13)
-#define JH7110_CLK_RTC (JH7110_CLK_END + 14)
-
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
#define JH7110_CLK_ISP_END 30
-/* external clocks */
-#define JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN (JH7110_CLK_ISP_END + 0)
-#define JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN (JH7110_CLK_ISP_END + 1)
-#define JH7110_ISP_TOP_CLK_BIST_APB_CLKGEN (JH7110_CLK_ISP_END + 2)
-#define JH7110_ISP_TOP_CLK_DVP_CLKGEN (JH7110_CLK_ISP_END + 3)
-
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
#define JH7110_CLK_VOUT_END 41
-/* external clocks */
-#define JH7110_HDMITX0_PIXELCLK (JH7110_CLK_VOUT_END + 0)
-#define JH7110_MIPITX_DPHY_RXESC (JH7110_CLK_VOUT_END + 1)
-#define JH7110_MIPITX_DPHY_TXBYTEHS (JH7110_CLK_VOUT_END + 2)
-
-
-
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
projects / platform / kernel / linux-starfive.git / commitdiff