Merge branch 'CR_1176_CLOCK_TREE_PLL_Xingyu.Wu' into 'jh7110-5.15.y-devel'
authorJason Zhou <jason.zhou@starfivetech.com>
Wed, 20 Jul 2022 09:28:58 +0000 (09:28 +0000)
committerJason Zhou <jason.zhou@starfivetech.com>
Wed, 20 Jul 2022 09:28:58 +0000 (09:28 +0000)
CR 1176 clock tree pll xingyu.wu

See merge request sdk/linux!280

1  2 
arch/riscv/boot/dts/starfive/jh7110.dtsi

                                "stg_apb", "clk_rtc",
                                "gmac0_rmii_refin", "gmac0_rgmii_rxin";
                        #clock-cells = <1>;
+                       starfive,sys-syscon = <&sys_syscon 0x18 0x1c
+                                       0x20 0x24 0x28 0x2c 0x30 0x34>;
                        status = "okay";
                };
  
                                 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
                                 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
                                 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
 -                               <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
 -                               <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
 -                               <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
                                 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
 -                               <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
 -                               <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
 -                               <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
 +                               <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
                        reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
                                        "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
 -                                      "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
 -                                      "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
 +                                      "rst_noc_disp","rst_noc_stg";
                        power-domains = <&pwrc JH7110_PD_VOUT>;
                };