arm64: dts: rockchip: Add WiFi support on px30-engicam

Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have
an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected
on the SDIO bus.

The SDIO power sequnce is connacted with exteernal 32KHz oscillator
and it require 3V3 regulator input.

This patch adds WiFi enablement nodes for these respective boards.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20201109181017.206834-6-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
index 8fdd7ff2fdf982f811e45fd978b9dcf64cc3eed6..0e1a93ec323402227c7364300abc55d19a7c9cc6 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
@@ -14,6 +14,51 @@
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
        };
+
+       sdio_pwrseq: sdio-pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               clocks = <&xin32k>;
+               clock-names = "ext_clock";
+               post-power-on-delay-ms = <80>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&wifi_enable_h>;
+       };
+
+       vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc3v3_rf_aux_mod";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-always-on;
+               regulator-boot-on;
+               vin-supply = <&vcc5v0_sys>;
+       };
+
+       xin32k: xin32k {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               clock-output-names = "xin32k";
+       };
+};
+
+&sdio {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       bus-width = <4>;
+       clock-frequency = <50000000>;
+       cap-sdio-irq;
+       cap-sd-highspeed;
+       keep-power-in-suspend;
+       mmc-pwrseq = <&sdio_pwrseq>;
+       non-removable;
+       sd-uhs-sdr104;
+       status = "okay";
+
+       brcmf: wifi@1 {
+               compatible = "brcm,bcm4329-fmac";
+               reg = <1>;
+       };
 };
 
 &gmac {

diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
index 58425b1e559f0ce45795c45fe1ff14ee5618215e..d5708779c28523662027a65736bbb8f02e540fcb 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi
@@ -6,3 +6,15 @@
  */
 
 #include "px30-engicam-common.dtsi"
+
+&pinctrl {
+       sdio-pwrseq {
+               wifi_enable_h: wifi-enable-h {
+                       rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+};
+
+&sdio_pwrseq {
+       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+};

diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
index e54d1e480daa116cf4e7d51a3fb0d82c99a0f340..913444548b59c794bf891ac0be129acf331e9c58 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts
@@ -19,3 +19,15 @@
                stdout-path = "serial2:115200n8";
        };
 };
+
+&pinctrl {
+       sdio-pwrseq {
+               wifi_enable_h: wifi-enable-h {
+                       rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+};
+
+&sdio_pwrseq {
+       reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
+};