arm64: tegra: Fix base address for SOR1 on Tegra194

The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index d15c4f0..a84a8b4 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1078,7 +1078,7 @@
 
                        sor1: sor@15b40000 {
                                compatible = "nvidia,tegra194-sor";
-                               reg = <0x155c0000 0x40000>;
+                               reg = <0x15b40000 0x40000>;
                                interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
                                         <&bpmp TEGRA194_CLK_SOR1_OUT>,