clk: exynos5433: add defines for HDMI-PHY output clocks
authorAndrzej Hajda <a.hajda@samsung.com>
Fri, 3 Apr 2015 13:20:52 +0000 (15:20 +0200)
committerSeung-Woo Kim <sw0312.kim@samsung.com>
Wed, 14 Dec 2016 04:45:48 +0000 (13:45 +0900)
HDMI driver must re-parent respective muxes during HDMI-PHY on/off to
HDMI-PHY output clocks. To reference those clocks their defines should be added.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
drivers/clk/samsung/clk-exynos5433.c
include/dt-bindings/clock/exynos5433.h

index bd2cd3c..2c2ac75 100644 (file)
@@ -2735,8 +2735,10 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
        FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
                        100000000),
        /* PHY clocks from HDMI_PHY */
-       FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
-       FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
+       FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
+                       NULL, CLK_IS_ROOT, 300000000),
+       FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
+                       NULL, CLK_IS_ROOT, 166000000),
 };
 
 static struct samsung_mux_clock disp_mux_clks[] __initdata = {
index ca61ceb..5e395da 100644 (file)
 #define CLK_SCLK_RGB_VCLK                              109
 #define CLK_SCLK_RGB_TV_VCLK                           110
 
-#define DISP_NR_CLK                                    111
+#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY              111
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY               112
+
+#define DISP_NR_CLK                                    113
 
 /* CMU_AUD */
 #define CLK_MOUT_AUD_PLL_USER                          1