drm/nouveau/therm/gk104: use split subdev type+inst in cg engine lists
authorBen Skeggs <bskeggs@redhat.com>
Thu, 4 Feb 2021 04:26:38 +0000 (14:26 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Thu, 11 Feb 2021 01:49:55 +0000 (11:49 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.c
drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.h

index a3a1e3593da0aecc52d39a1394126df6518468bf..45e295c271fb5baed46646861d80a4428efd17bb 100644 (file)
@@ -35,8 +35,8 @@ gk104_clkgate_enable(struct nvkm_therm *base)
        int i;
 
        /* Program ENG_MANT, ENG_FILTER */
-       for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) {
-               if (!nvkm_device_subdev(dev, order[i].engine, 0))
+       for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) {
+               if (!nvkm_device_subdev(dev, order[i].type, order[i].inst))
                        continue;
 
                nvkm_mask(dev, 0x20200 + order[i].offset, 0xff00, 0x4500);
@@ -47,8 +47,8 @@ gk104_clkgate_enable(struct nvkm_therm *base)
        nvkm_wr32(dev, 0x02028c, therm->idle_filter->hubmmu);
 
        /* Enable clockgating (ENG_CLK = RUN->AUTO) */
-       for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) {
-               if (!nvkm_device_subdev(dev, order[i].engine, 0))
+       for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) {
+               if (!nvkm_device_subdev(dev, order[i].type, order[i].inst))
                        continue;
 
                nvkm_mask(dev, 0x20200 + order[i].offset, 0x00ff, 0x0045);
@@ -64,8 +64,8 @@ gk104_clkgate_fini(struct nvkm_therm *base, bool suspend)
        int i;
 
        /* ENG_CLK = AUTO->RUN, ENG_PWR = RUN->AUTO */
-       for (i = 0; order[i].engine != NVKM_SUBDEV_NR; i++) {
-               if (!nvkm_device_subdev(dev, order[i].engine, 0))
+       for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) {
+               if (!nvkm_device_subdev(dev, order[i].type, order[i].inst))
                        continue;
 
                nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54);
@@ -73,15 +73,15 @@ gk104_clkgate_fini(struct nvkm_therm *base, bool suspend)
 }
 
 const struct gk104_clkgate_engine_info gk104_clkgate_engine_info[] = {
-       { NVKM_ENGINE_GR,     0x00 },
-       { NVKM_ENGINE_MSPDEC, 0x04 },
-       { NVKM_ENGINE_MSPPP,  0x08 },
-       { NVKM_ENGINE_MSVLD,  0x0c },
-       { NVKM_ENGINE_CE0,    0x10 },
-       { NVKM_ENGINE_CE1,    0x14 },
-       { NVKM_ENGINE_MSENC,  0x18 },
-       { NVKM_ENGINE_CE2,    0x1c },
-       { NVKM_SUBDEV_NR, 0 },
+       { NVKM_ENGINE_GR,     0, 0x00 },
+       { NVKM_ENGINE_MSPDEC, 0, 0x04 },
+       { NVKM_ENGINE_MSPPP,  0, 0x08 },
+       { NVKM_ENGINE_MSVLD,  0, 0x0c },
+       { NVKM_ENGINE_CE,     0, 0x10 },
+       { NVKM_ENGINE_CE,     1, 0x14 },
+       { NVKM_ENGINE_MSENC,  0, 0x18 },
+       { NVKM_ENGINE_CE,     2, 0x1c },
+       { NVKM_SUBDEV_NR },
 };
 
 const struct gf100_idle_filter gk104_idle_filter = {
index 293e7743b19bb2357064e22fe642ec741b4426cd..9a8641421038f3048404dbd0fb22fcb929037963 100644 (file)
@@ -31,7 +31,8 @@
 #include "gf100.h"
 
 struct gk104_clkgate_engine_info {
-       enum nvkm_devidx engine;
+       enum nvkm_subdev_type type;
+       int inst;
        u8 offset;
 };