re PR c++/12727 (mipsisa64-elf -mips32 regression: g++.dg/eh/registers1.C)

	PR target/12727
	* config/mips/mips.c (mips_save_reg): Fix frame information for sdc1
	on 32-bit big-endian targets.

From-SVN: r74071

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d0ea86b..f9bbca2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2003-11-30  Richard Sandiford  <rsandifo@redhat.com>
+
+       PR target/12727
+       * config/mips/mips.c (mips_save_reg): Fix frame information for sdc1
+       on 32-bit big-endian targets.
+
 2003-11-30  Kazu Hirata  <kazu@cs.umass.edu>
 
        * genemit.c (register_constraints): Remove.

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 6096edd..87e2089 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -6543,11 +6543,15 @@ mips_frame_set (rtx mem, rtx reg)
 static void
 mips_save_reg (rtx reg, rtx mem)
 {
-  if (GET_MODE (reg) == DFmode && mips_split_64bit_move_p (mem, reg))
+  if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
     {
       rtx x1, x2;
 
-      mips_split_64bit_move (mem, reg);
+      if (mips_split_64bit_move_p (mem, reg))
+       mips_split_64bit_move (mem, reg);
+      else
+       emit_move_insn (mem, reg);
+
       x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
       x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
       mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));