unsigned int scu_get_core_count(void __iomem *);
int scu_power_mode(void __iomem *, unsigned int);
int scu_cpu_power_enable(void __iomem *, unsigned int);
+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu);
#else
static inline unsigned int scu_get_core_count(void __iomem *scu_base)
{
{
return -EINVAL;
}
+static inline int scu_get_cpu_power_mode(void __iomem *scu_base,
+ unsigned int logical_cpu)
+{
+ return -EINVAL;
+}
#endif
#if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
#define SCU_STANDBY_ENABLE (1 << 5)
#define SCU_CONFIG 0x04
#define SCU_CPU_STATUS 0x08
+#define SCU_CPU_STATUS_MASK GENMASK(1, 0)
#define SCU_INVALIDATE 0x0c
#define SCU_FPGA_REVISION 0x10
if (mode > 3 || mode == 1 || cpu > 3)
return -EINVAL;
- val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
+ val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
+ val &= ~SCU_CPU_STATUS_MASK;
val |= mode;
writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
{
return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
}
+
+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)
+{
+ unsigned int val;
+ int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
+
+ if (cpu > 3)
+ return -EINVAL;
+
+ val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
+ val &= SCU_CPU_STATUS_MASK;
+
+ return val;
+}