drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4
authorTvrtko Ursulin <tvrtko.ursulin@intel.com>
Wed, 17 Jul 2019 18:06:23 +0000 (19:06 +0100)
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>
Fri, 19 Jul 2019 14:35:21 +0000 (15:35 +0100)
Having fixed the incorect MCR programming in an earlier patch, we can now
stop ignoring read back of GEN8_L3SQCREG4 during engine workaround
verification.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717180624.20354-6-tvrtko.ursulin@linux.intel.com
drivers/gpu/drm/i915/gt/intel_workarounds.c

index 619d42a..ff532ff 100644 (file)
@@ -177,19 +177,6 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
        wa_write_masked_or(wal, reg, val, val);
 }
 
-static void
-ignore_wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val)
-{
-       struct i915_wa wa = {
-               .reg  = reg,
-               .mask = mask,
-               .val  = val,
-               /* Bonkers HW, skip verifying */
-       };
-
-       _wa_add(wal, &wa);
-}
-
 #define WA_SET_BIT_MASKED(addr, mask) \
        wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
 
@@ -1260,10 +1247,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                             _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
 
                /* WaPipelineFlushCoherentLines:icl */
-               ignore_wa_write_or(wal,
-                                  GEN8_L3SQCREG4,
-                                  GEN8_LQSC_FLUSH_COHERENT_LINES,
-                                  GEN8_LQSC_FLUSH_COHERENT_LINES);
+               wa_write_or(wal,
+                           GEN8_L3SQCREG4,
+                           GEN8_LQSC_FLUSH_COHERENT_LINES);
 
                /*
                 * Wa_1405543622:icl
@@ -1290,10 +1276,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                 * Wa_1405733216:icl
                 * Formerly known as WaDisableCleanEvicts
                 */
-               ignore_wa_write_or(wal,
-                                  GEN8_L3SQCREG4,
-                                  GEN11_LQSC_CLEAN_EVICT_DISABLE,
-                                  GEN11_LQSC_CLEAN_EVICT_DISABLE);
+               wa_write_or(wal,
+                           GEN8_L3SQCREG4,
+                           GEN11_LQSC_CLEAN_EVICT_DISABLE);
 
                /* WaForwardProgressSoftReset:icl */
                wa_write_or(wal,