+2008-05-28 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * config/s390/s390.c (z10_cost): New cost function for z10.
+ (s390_handle_arch_option, override_options): Support
+ -march=z10 switch.
+ (s390_issue_rate): Adjust issue rate for z10.
+ * config/s390/s390.h (processor_type): Add PROCESSOR_2097_Z10.
+ (processor_flags): Add PF_Z10.
+ (TARGET_CPU_Z10, TARGET_Z10): New macro definitions.
+ * config/s390/s390.md (cpu, cpu_facility attributes): Add z10.
+ * gcc/config.gcc: Add z10.
+
2008-05-28 Richard Guenther <rguenther@suse.de>
PR tree-optimization/36291
COSTS_N_INSNS (24), /* DSGR */
};
+static const
+struct processor_costs z10_cost =
+{
+ COSTS_N_INSNS (4), /* M */
+ COSTS_N_INSNS (2), /* MGHI */
+ COSTS_N_INSNS (2), /* MH */
+ COSTS_N_INSNS (2), /* MHI */
+ COSTS_N_INSNS (4), /* ML */
+ COSTS_N_INSNS (4), /* MR */
+ COSTS_N_INSNS (5), /* MS */
+ COSTS_N_INSNS (6), /* MSG */
+ COSTS_N_INSNS (4), /* MSGF */
+ COSTS_N_INSNS (4), /* MSGFR */
+ COSTS_N_INSNS (4), /* MSGR */
+ COSTS_N_INSNS (4), /* MSR */
+ COSTS_N_INSNS (1), /* multiplication in DFmode */
+ COSTS_N_INSNS (28), /* MXBR */
+ COSTS_N_INSNS (130), /* SQXBR */
+ COSTS_N_INSNS (66), /* SQDBR */
+ COSTS_N_INSNS (38), /* SQEBR */
+ COSTS_N_INSNS (1), /* MADBR */
+ COSTS_N_INSNS (1), /* MAEBR */
+ COSTS_N_INSNS (60), /* DXBR */
+ COSTS_N_INSNS (40), /* DDBR */
+ COSTS_N_INSNS (26), /* DEBR */
+ COSTS_N_INSNS (30), /* DLGR */
+ COSTS_N_INSNS (23), /* DLR */
+ COSTS_N_INSNS (23), /* DR */
+ COSTS_N_INSNS (24), /* DSGFR */
+ COSTS_N_INSNS (24), /* DSGR */
+};
+
extern int reload_completed;
/* Save information from a "cmpxx" operation until the branch or scc is
| PF_LONG_DISPLACEMENT | PF_EXTIMM},
{"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
| PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
+ {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
+ | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
};
size_t i;
}
/* Set processor cost function. */
- if (s390_tune == PROCESSOR_2094_Z9_109)
- s390_cost = &z9_109_cost;
- else if (s390_tune == PROCESSOR_2084_Z990)
- s390_cost = &z990_cost;
- else
- s390_cost = &z900_cost;
-
+ switch (s390_tune)
+ {
+ case PROCESSOR_2084_Z990:
+ s390_cost = &z990_cost;
+ break;
+ case PROCESSOR_2094_Z9_109:
+ s390_cost = &z9_109_cost;
+ break;
+ case PROCESSOR_2097_Z10:
+ s390_cost = &z10_cost;
+ break;
+ default:
+ s390_cost = &z900_cost;
+ }
+
if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
error ("-mbackchain -mpacked-stack -mhard-float are not supported "
"in combination");
static int
s390_issue_rate (void)
{
- if (s390_tune == PROCESSOR_2084_Z990
- || s390_tune == PROCESSOR_2094_Z9_109)
- return 3;
- return 1;
+ switch (s390_tune)
+ {
+ case PROCESSOR_2084_Z990:
+ case PROCESSOR_2094_Z9_109:
+ return 3;
+ case PROCESSOR_2097_Z10:
+ return 2;
+ default:
+ return 1;
+ }
}
static int
;; distinguish between g5 and g6, but there are differences between the two
;; CPUs could in theory be modeled.
-(define_attr "cpu" "g5,g6,z900,z990,z9_109"
+(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
(const (symbol_ref "s390_tune")))
-(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp"
+(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
(const_string "standard"))
(define_attr "enabled" ""
(and (eq_attr "cpu_facility" "dfp")
(ne (symbol_ref "TARGET_DFP") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "z10")
+ (ne (symbol_ref "TARGET_Z10") (const_int 0)))
(const_int 1)]
(const_int 0)))