deinterlace: Add AFBC support on TL1 [1/1]

PD#SWPL-3113

Problem:
Add AFBC support on TL1

Solution:
Add AFBC support on TL1

Verify:
T962x2-x301

Change-Id: Ib4f40f6ca0cbb1553bf4f76848d1649822dda3e8
Signed-off-by: huaihao.guo <huaihao.guo@amlogic.com>

diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c
index c613cd9..8039a08 100644 (file)
--- a/drivers/amlogic/media/deinterlace/deinterlace.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace.c
@@ -129,7 +129,7 @@ static di_dev_t *de_devp;
 static dev_t di_devno;
 static struct class *di_clsp;
 
-static const char version_s[] = "2018-12-07a";
+static const char version_s[] = "2018-12-12a";
 
 static int bypass_state = 1;
 static int bypass_all;

diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
index a7e6bf9..b387f77 100644 (file)
--- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c
+++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c
@@ -960,8 +960,9 @@ static enum eAFBC_DEC afbc_get_decnub(void)
                sel_dec = eAFBC_DEC1;
        else if (is_meson_g12a_cpu())
                sel_dec = AFBC_DEC_SEL;
-
-
+       /* TL1 only have AFBC0 */
+       else if (is_meson_tl1_cpu())
+               sel_dec = eAFBC_DEC0;
        return sel_dec;
 }
 
@@ -976,9 +977,9 @@ bool afbc_is_supported(void)
 
        /*currently support txlx and g12a*/
        if (is_meson_txlx_cpu()
-               || is_meson_g12a_cpu())
+               || is_meson_g12a_cpu()
+               || is_meson_tl1_cpu())
                ret = true;
-
        return ret;
 
 }
@@ -1024,7 +1025,19 @@ void enable_afbc_input(struct vframe_s *vf)
                out_height = h_aligned>>1;
        }
        RDMA_WR(reg[eAFBC_MODE], r);
-       RDMA_WR(reg[eAFBC_CONV_CTRL], 0x100);
+       r = 0x100;
+       /* TL1 add bit[13:12]: fmt_mode; 0:yuv444; 1:yuv422; 2:yuv420
+        * di does not support yuv444, so for fmt yuv444 di will bypass+
+        */
+       if (is_meson_tl1_cpu()) {
+               if (vf->type & VIDTYPE_VIU_444)
+                       r |= (0 << 12);
+               else if (vf->type & VIDTYPE_VIU_422)
+                       r |= (1 << 12);
+               else
+                       r |= (2 << 12);
+       }
+       RDMA_WR(reg[eAFBC_CONV_CTRL], r);
        u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3;
        v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3;
        RDMA_WR(reg[eAFBC_DEC_DEF_COLOR],
@@ -1103,10 +1116,15 @@ static void afbcx_sw(bool on)   /*g12a*/
                        (reg_ctrl == VD1_AFBCD0_MISC_CTRL)?0:1, 8, 1);
                RDMA_WR(reg_en, 0x1600);
                RDMA_WR_BITS(VIUB_MISC_CTRL0, 1, 16, 1);
+               /*TL1 add mem control bit */
+               if (is_meson_tl1_cpu())
+                       RDMA_WR_BITS(VD1_AFBCD0_MISC_CTRL, 1, 22, 1);
        } else {
                RDMA_WR(reg_ctrl, tmp);
                RDMA_WR(reg_en, 0x1600);
                RDMA_WR_BITS(VIUB_MISC_CTRL0, 0, 16, 1);
+               if (is_meson_tl1_cpu())
+                       RDMA_WR_BITS(VD1_AFBCD0_MISC_CTRL, 0, 22, 1);
        }
 //     printk("%s,on[%d],CTRL[0x%x],en[0x%x]\n", __func__, on,
 //                     RDMA_RD(VD1_AFBCD0_MISC_CTRL),