drm/amd/display: Clean up some inconsistent indenting
authorJiapeng Chong <jiapeng.chong@linux.alibaba.com>
Tue, 26 Jul 2022 07:25:50 +0000 (15:25 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 28 Jul 2022 20:05:15 +0000 (16:05 -0400)
No functional modification involved.

smatch warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:1728 dcn20_program_front_end_for_ctx() warn: inconsistent indenting.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

index 3e44b79..884fa06 100644 (file)
@@ -1716,15 +1716,13 @@ void dcn20_program_front_end_for_ctx(
        DC_LOGGER_INIT(dc->ctx->logger);
 
        /* Carry over GSL groups in case the context is changing. */
-       for (i = 0; i < dc->res_pool->pipe_count; i++) {
-               struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-               struct pipe_ctx *old_pipe_ctx =
-                       &dc->current_state->res_ctx.pipe_ctx[i];
-
-               if (pipe_ctx->stream == old_pipe_ctx->stream)
-                       pipe_ctx->stream_res.gsl_group =
-                               old_pipe_ctx->stream_res.gsl_group;
-       }
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+               struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
+
+               if (pipe_ctx->stream == old_pipe_ctx->stream)
+                       pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group;
+       }
 
        if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
                for (i = 0; i < dc->res_pool->pipe_count; i++) {