{VPU_TCON, HHI_VPU_MEM_PD_REG3, 0x3, 16, 16},
{VPU_AXI_WR1, HHI_VPU_MEM_PD_REG4, 0x3, 0, 2},
{VPU_AXI_WR0, HHI_VPU_MEM_PD_REG4, 0x3, 2, 2},
- {VPU_DMA, HHI_VPU_MEM_PD_REG4, 0xf, 4, 4},
+ {VPU_AFBCE, HHI_VPU_MEM_PD_REG4, 0x3, 4, 2},
+ {VPU_VDIN_WR_MIF2, HHI_VPU_MEM_PD_REG4, 0x3, 6, 2},
+ {VPU_DMA, HHI_VPU_MEM_PD_REG4, 0xf, 8, 4},
{VPU_MOD_MAX, VPU_REG_END, 0, 0, 0},
};
VPU_AXI_WR1, /* reg4[1:0], TL1 */
VPU_AXI_WR0, /* reg4[3:2], TL1 */
VPU_AFBCE, /* reg4[5:4], TL1 */
- VPU_DMA, /* reg4[7:4], TM2 */
+ VPU_VDIN_WR_MIF2, /* reg4[7:6], TM2 */
+ VPU_DMA, /* reg4[11:8], TM2 */
VPU_MOD_MAX,