arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes

Add PCIe controller and PHY nodes for sc7280 SOC.

Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1633628923-25047-3-git-send-email-pmaliset@codeaurora.org

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index d43f82c..d1a6275 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1568,6 +1568,117 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               pcie1: pci@1c08000 {
+                       compatible = "qcom,pcie-sc7280";
+                       reg = <0 0x01c08000 0 0x3000>,
+                             <0 0x40000000 0 0xf1d>,
+                             <0 0x40000f20 0 0xa8>,
+                             <0 0x40001000 0 0x1000>,
+                             <0 0x40100000 0 0x100000>;
+
+                       reg-names = "parf", "dbi", "elbi", "atu", "config";
+                       device_type = "pci";
+                       linux,pci-domain = <1>;
+                       bus-range = <0x00 0xff>;
+                       num-lanes = <2>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+                                <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+
+                       interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+                                <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
+                                <&pcie1_lane 0>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_PCIE_1_AUX_CLK>,
+                                <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+                                <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+                                <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+                                <&gcc GCC_DDRSS_PCIE_SF_CLK>;
+
+                       clock-names = "pipe",
+                                     "pipe_mux",
+                                     "phy_pipe",
+                                     "ref",
+                                     "aux",
+                                     "cfg",
+                                     "bus_master",
+                                     "bus_slave",
+                                     "slave_q2a",
+                                     "tbu",
+                                     "ddrss_sf_tbu";
+
+                       assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+                       assigned-clock-rates = <19200000>;
+
+                       resets = <&gcc GCC_PCIE_1_BCR>;
+                       reset-names = "pci";
+
+                       power-domains = <&gcc GCC_PCIE_1_GDSC>;
+
+                       phys = <&pcie1_lane>;
+                       phy-names = "pciephy";
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pcie1_clkreq_n>;
+
+                       iommus = <&apps_smmu 0x1c80 0x1>;
+
+                       iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+                                   <0x100 &apps_smmu 0x1c81 0x1>;
+
+                       status = "disabled";
+               };
+
+               pcie1_phy: phy@1c0e000 {
+                       compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
+                       reg = <0 0x01c0e000 0 0x1c0>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+                                <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_CLKREF_EN>,
+                                <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
+                       clock-names = "aux", "cfg_ahb", "ref", "refgen";
+
+                       resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+                       reset-names = "phy";
+
+                       assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
+                       assigned-clock-rates = <100000000>;
+
+                       status = "disabled";
+
+                       pcie1_lane: lanes@1c0e200 {
+                               reg = <0 0x01c0e200 0 0x170>,
+                                     <0 0x01c0e400 0 0x200>,
+                                     <0 0x01c0ea00 0 0x1f0>,
+                                     <0 0x01c0e600 0 0x170>,
+                                     <0 0x01c0e800 0 0x200>,
+                                     <0 0x01c0ee00 0 0xf4>;
+                               clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
+                               clock-names = "pipe0";
+
+                               #phy-cells = <0>;
+                               #clock-cells = <1>;
+                               clock-output-names = "pcie_1_pipe_clk";
+                       };
+               };
+
                ipa: ipa@1e40000 {
                        compatible = "qcom,sc7280-ipa";
 
@@ -2686,6 +2797,13 @@
                        gpio-ranges = <&tlmm 0 0 175>;
                        wakeup-parent = <&pdc>;
 
+                       pcie1_clkreq_n: pcie1-clkreq-n {
+                               pins = "gpio79";
+                               function = "pcie1_clkreqn";
+                               drive-strength = <2>;
+                               bias-pull-up;
+                       };
+
                        qspi_clk: qspi-clk {
                                pins = "gpio14";
                                function = "qspi_clk";