drm/i915: HSW PM Frequency bits fix

According to HSW PM programming guide, frequency bits starts at
24 instead of 25.

v2: Paulo Zanoni noticed that only frequency bits can be set at
GEN6_RPNSWREQ. All others are read only.

CC: Ben Widawsky <ben@bwidawsk.net>
CC: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bceca11..5e995ec 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4190,6 +4190,7 @@
 #define GEN6_RPNSWREQ                          0xA008
 #define   GEN6_TURBO_DISABLE                   (1<<31)
 #define   GEN6_FREQUENCY(x)                    ((x)<<25)
+#define   HSW_FREQUENCY(x)                     ((x)<<24)
 #define   GEN6_OFFSET(x)                       ((x)<<19)
 #define   GEN6_AGGRESSIVE_TURBO                        (0<<15)
 #define GEN6_RC_VIDEO_FREQ                     0xA00C

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6fa9b79..27f94cd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2460,10 +2460,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
        if (val == dev_priv->rps.cur_delay)
                return;
 
-       I915_WRITE(GEN6_RPNSWREQ,
-                  GEN6_FREQUENCY(val) |
-                  GEN6_OFFSET(0) |
-                  GEN6_AGGRESSIVE_TURBO);
+       if (IS_HASWELL(dev))
+               I915_WRITE(GEN6_RPNSWREQ,
+                          HSW_FREQUENCY(val));
+       else
+               I915_WRITE(GEN6_RPNSWREQ,
+                          GEN6_FREQUENCY(val) |
+                          GEN6_OFFSET(0) |
+                          GEN6_AGGRESSIVE_TURBO);
 
        /* Make sure we continue to get interrupts
         * until we hit the minimum or maximum frequencies.
@@ -2601,12 +2605,19 @@ static void gen6_enable_rps(struct drm_device *dev)
                   GEN6_RC_CTL_EI_MODE(1) |
                   GEN6_RC_CTL_HW_ENABLE);
 
-       I915_WRITE(GEN6_RPNSWREQ,
-                  GEN6_FREQUENCY(10) |
-                  GEN6_OFFSET(0) |
-                  GEN6_AGGRESSIVE_TURBO);
-       I915_WRITE(GEN6_RC_VIDEO_FREQ,
-                  GEN6_FREQUENCY(12));
+       if (IS_HASWELL(dev)) {
+               I915_WRITE(GEN6_RPNSWREQ,
+                          HSW_FREQUENCY(10));
+               I915_WRITE(GEN6_RC_VIDEO_FREQ,
+                          HSW_FREQUENCY(12));
+       } else {
+               I915_WRITE(GEN6_RPNSWREQ,
+                          GEN6_FREQUENCY(10) |
+                          GEN6_OFFSET(0) |
+                          GEN6_AGGRESSIVE_TURBO);
+               I915_WRITE(GEN6_RC_VIDEO_FREQ,
+                          GEN6_FREQUENCY(12));
+       }
 
        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
        I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,