EVT SetCCResultType =
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ unsigned BitWidth = VT.getScalarSizeInBits();
if (Opcode == ISD::USUBSAT && !TLI.isOperationLegal(ISD::UMAX, VT)) {
+ // Handle a special-case with a bit-hack instead of cmp+select:
+ // usubsat X, SMIN --> (X ^ SMIN) & (X s>> BW-1)
+ ConstantSDNode *C = isConstOrConstSplat(Y, true);
+ if (C && C->getAPIntValue().isSignMask()) {
+ SDValue SignMask = DAG.getConstant(C->getAPIntValue(), DL, VT);
+ SDValue ShiftAmt = DAG.getConstant(BitWidth - 1, DL, VT);
+ SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, X, SignMask);
+ SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShiftAmt);
+ return DAG.getNode(ISD::AND, DL, VT, Xor, Sra);
+ }
+
// usubsat X, Y --> (X >u Y) ? X - Y : 0
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, X, Y);
SDValue Cmp = DAG.getSetCC(DL, SetCCResultType, X, Y, ISD::SETUGT);
if ((Opcode == ISD::SADDSAT || Opcode == ISD::SSUBSAT) &&
(!VT.isVector() || VT == MVT::v2i64)) {
- unsigned BitWidth = VT.getScalarSizeInBits();
APInt MinVal = APInt::getSignedMinValue(BitWidth);
APInt MaxVal = APInt::getSignedMaxValue(BitWidth);
SDValue Zero = DAG.getConstant(0, DL, VT);
}
; This is logically equivalent to the above.
+; usubsat X, (1 << (BW-1)) <--> (X ^ (1 << (BW-1))) & (ashr X, (BW-1))
define <8 x i16> @ashr_xor_and(<8 x i16> %x) nounwind {
; SSE-LABEL: ashr_xor_and:
ret <4 x i32> %res
}
+; usubsat X, (1 << (BW-1)) <--> (X ^ (1 << (BW-1))) & (ashr X, (BW-1))
+
define <4 x i32> @usubsat_custom(<4 x i32> %x) nounwind {
; SSE2OR3-LABEL: usubsat_custom:
; SSE2OR3: # %bb.0:
-; SSE2OR3-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
-; SSE2OR3-NEXT: pxor %xmm0, %xmm1
-; SSE2OR3-NEXT: pxor %xmm2, %xmm2
-; SSE2OR3-NEXT: pcmpgtd %xmm2, %xmm1
-; SSE2OR3-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2OR3-NEXT: movdqa %xmm0, %xmm1
+; SSE2OR3-NEXT: psrad $31, %xmm1
+; SSE2OR3-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2OR3-NEXT: pand %xmm1, %xmm0
; SSE2OR3-NEXT: retq
;