clk: imx6q: add DCICx clocks gate
authorAnson Huang <anson.huang@nxp.com>
Fri, 30 Nov 2018 06:31:40 +0000 (06:31 +0000)
committerStephen Boyd <sboyd@kernel.org>
Mon, 10 Dec 2018 19:34:50 +0000 (11:34 -0800)
On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks
gate in CCM_CCGR0 register, add them into clock tree for
clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/imx/clk-imx6q.c
include/dt-bindings/clock/imx6qdl-clock.h

index bbe0c60..31a9d94 100644 (file)
@@ -737,6 +737,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk[IMX6QDL_CLK_CAN1_SERIAL]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
        clk[IMX6QDL_CLK_CAN2_IPG]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
        clk[IMX6QDL_CLK_CAN2_SERIAL]  = imx_clk_gate2("can2_serial",   "can_root",          base + 0x68, 20);
+       clk[IMX6QDL_CLK_DCIC1]        = imx_clk_gate2("dcic1",         "ipu1_podf",         base + 0x68, 24);
+       clk[IMX6QDL_CLK_DCIC2]        = imx_clk_gate2("dcic2",         "ipu2_podf",         base + 0x68, 26);
        clk[IMX6QDL_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
        clk[IMX6QDL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
        clk[IMX6QDL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
index 87b068f..b3cef29 100644 (file)
 #define IMX6QDL_CLK_EPIT1                      261
 #define IMX6QDL_CLK_EPIT2                      262
 #define IMX6QDL_CLK_MMDC_P0_IPG                        263
-#define IMX6QDL_CLK_END                                264
+#define IMX6QDL_CLK_DCIC1                      264
+#define IMX6QDL_CLK_DCIC2                      265
+#define IMX6QDL_CLK_END                                266
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */