bool object_preemption;
bool has_uint_rt;
+ /**
+ * DEPTH and STENCIL attachment write state for Wa_18019816803.
+ */
+ bool ds_write_state;
+
uint32_t n_occlusion_queries;
};
}
#endif
+ /* Check if blorp ds state matches ours. */
+ if (intel_needs_workaround(cmd_buffer->device->info, 18019816803)) {
+ bool blorp_ds_state = params->depth.enabled || params->stencil.enabled;
+ if (cmd_buffer->state.gfx.ds_write_state != blorp_ds_state) {
+ batch->flags |= BLORP_BATCH_NEED_PSS_STALL_SYNC;
+ cmd_buffer->state.gfx.ds_write_state = blorp_ds_state;
+ }
+ }
+
if (params->depth.enabled &&
!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
genX(cmd_buffer_emit_gfx12_depth_wa)(cmd_buffer, ¶ms->depth.surf);
primary->state.current_l3_config = NULL;
primary->state.current_hash_scale = 0;
primary->state.gfx.push_constant_stages = 0;
+ primary->state.gfx.ds_write_state = false;
vk_dynamic_graphics_state_dirty_all(&primary->vk.dynamic_graphics_state);
/* Each of the secondary command buffers will use its own state base
ds.BackfaceStencilTestFunction = genX(vk_to_intel_compare_op)[opt_ds.stencil.back.op.compare];
}
+#if INTEL_NEEDS_WA_18019816803
+ if (intel_needs_workaround(cmd_buffer->device->info, 18019816803)) {
+ bool ds_write_state = opt_ds.depth.write_enable || opt_ds.stencil.write_enable;
+ if (cmd_buffer->state.gfx.ds_write_state != ds_write_state) {
+ genX(batch_emit_pipe_control)(&cmd_buffer->batch, cmd_buffer->device->info,
+ ANV_PIPE_PSS_STALL_SYNC_BIT);
+ cmd_buffer->state.gfx.ds_write_state = ds_write_state;
+ }
+ }
+#endif
+
const bool pma = want_stencil_pma_fix(cmd_buffer, &opt_ds);
genX(cmd_buffer_enable_pma_fix)(cmd_buffer, pma);
}