* config/tc-i370.c: Fix formatting.
* config/tc-i960.c: Likewise.
* config/tc-m68k.c: Likewise.
+2000-09-11 Kazu Hirata <kazu@hxi.com>
+
+ * config/tc-i370.c: Fix formatting.
+ * config/tc-i960.c: Likewise.
+ * config/tc-m68k.c: Likewise.
+
2000-09-09 Philip Blundell <philb@gnu.org>
* configure.in (arm*-*-uclinux*): New target.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA. */
+ 02111-1307, USA. */
/* This assembler implements a very hacked version of an elf-like thing
* that gcc emits (when gcc is suitably hacked). To make it behave more
as in 0d1.0. */
const char FLT_CHARS[] = "dD";
-
void
md_show_usage (stream)
FILE *stream;
static void i370_elf_validate_fix PARAMS ((fixS *, segT));
#endif
-
\f
/* The target specific pseudo-ops which we support. */
1. r<reg_num> which has the value <reg_num>.
2. r.<reg_num> which has the value <reg_num>.
-
Each floating point register has predefined names of the form:
1. f<reg_num> which has the value <reg_num>.
2. f.<reg_num> which has the value <reg_num>.
There are only four floating point registers, and these are
commonly labelled 0,2,4 and 6. Thus, there is no f1, f3, etc.
-
There are individual registers as well:
rbase or r.base has the value 3 (base register)
rpgt or r.pgt has the value 4 (page origin table pointer)
dsa or r.dsa has the value 13 (stack pointer)
lr has the value 14 (link reg)
- The table is sorted. Suitable for searching by a binary search. */
+ The table is sorted. Suitable for searching by a binary search. */
static const struct pd_reg pre_defined_registers[] =
{
{ "f4", 4 },
{ "f6", 6 },
-
{ "dsa",13 }, /* stack pointer */
{ "lr", 14 }, /* Link Register */
{ "pgt", 4 }, /* Page Origin Table Pointer */
\f
/* Set i370_cpu if it is not already set.
Currently defaults to the reasonable superset;
- but can be made more fine grained if desred. */
+ but can be made more fine grained if desred. */
static void
i370_set_cpu ()
const char *default_os = TARGET_OS;
const char *default_cpu = TARGET_CPU;
- /* override with the superset for the moment. */
+ /* override with the superset for the moment. */
i370_cpu = I370_OPCODE_ESA390_SUPERSET;
if (i370_cpu == 0)
{
i370_set_cpu ();
#ifdef OBJ_ELF
- /* Set the ELF flags if desired. */
+ /* Set the ELF flags if desired. */
if (i370_flags)
bfd_set_private_flags (stdoutput, i370_flags);
#endif
return BFD_RELOC_UNUSED;
}
-/* Like normal .long/.short/.word, except support @got, etc. */
-/* clobbers input_line_pointer, checks end-of-line. */
+/* Like normal .long/.short/.word, except support @got, etc. */
+/* clobbers input_line_pointer, checks end-of-line. */
static void
i370_elf_cons (nbytes)
register int nbytes; /* 1=.byte, 2=.word, 4=.long */
}
while (*input_line_pointer++ == ',');
- input_line_pointer--; /* Put terminator back into stream. */
+ input_line_pointer--; /* Put terminator back into stream. */
demand_empty_rest_of_line ();
}
}
#endif /* OBJ_ELF */
-
\f
#define LITERAL_POOL_SUPPORT
#ifdef LITERAL_POOL_SUPPORT
-/* Provide support for literal pools within the text section. */
+/* Provide support for literal pools within the text section. */
/* Loosely based on similar code from tc-arm.c */
/*
* We will use four symbols to locate four parts of the literal pool.
expression (exx);
/* OK, now we have to subtract the "using" location */
- /* normally branches appear in the text section only... */
+ /* normally branches appear in the text section only... */
if (0 == strncmp (now_seg->name, ".text", 5) || 0 > i370_using_other_regno)
{
i370_make_relative (exx, &i370_using_text_baseaddr);
else as_bad ("bad alignment of %d bytes in literal pool", biggest_literal_size);
if (0 == biggest_align) biggest_align = 1;
-
/* Align pool for short, word, double word accesses */
frag_align (biggest_align, 0, 0);
record_alignment (now_seg, biggest_align);
/* Note that the gas listing will print only the first five
* entries in the pool .... wonder how to make it print more ...
*/
- /* output largest literals first, then the smaller ones. */
+ /* output largest literals first, then the smaller ones. */
for (litsize=8; litsize; litsize /=2)
{
symbolS *current_poolP = NULL;
char *star;
/* if "*" appears in a using, it means "." */
- /* replace it with "." so that expr doesn't get confused. */
+ /* replace it with "." so that expr doesn't get confused. */
star = strchr (input_line_pointer, '*');
if (star)
*star = '.';
/* the first arg to using will usually be ".", but it can
- * be a more complex exprsssion too ... */
+ * be a more complex exprsssion too ... */
expression (&baseaddr);
if (star)
*star = '*';
hold = input_line_pointer;
input_line_pointer = str;
- /* register names are only allowed where there are registers ... */
+ /* register names are only allowed where there are registers ... */
if ((operand->flags & I370_OPERAND_GPR) != 0)
{
/* quickie hack to get past things like (,r13) */
/* check for a address constant expression */
/* We will put PSW-relative addresses in the text section,
- * and adress literals in the .data (or other) section. */
+ * and adress literals in the .data (or other) section. */
else if (i370_addr_cons (&ex))
use_other=1;
else if (i370_addr_offset (&ex))
/* Allow @HA, @L, @H on constants.
* Well actually, no we don't; there really don't make sense
* (at least not to me) for the i370. However, this code is
- * left here for any dubious future expansion reasons ... */
+ * left here for any dubious future expansion reasons ... */
char *orig_str = str;
if ((reloc = i370_elf_suffix (&str, &ex)) != BFD_RELOC_UNUSED)
}
/* 360/370/390 have two float formats: an old, funky 360 single-precision
- * format, and the ieee format. Support only the ieee format. */
+ * format, and the ieee format. Support only the ieee format. */
t = atof_ieee (input_line_pointer, type, words);
if (t)
input_line_pointer = t;
return fixp->fx_frag->fr_address + fixp->fx_where;
}
-
/* Apply a fixup to the object code. This is called for all the
fixups we generated by the call to fix_new_exp, above. In the call
above we used a reloc code which was the largest legal reloc code
#endif
/* Fetch the instruction, insert the fully resolved operand
value, and stuff the instruction back again.
- fisxp->fx_size is the length of the instruction. */
+ fisxp->fx_size is the length of the instruction. */
where = fixp->fx_frag->fr_literal + fixp->fx_where;
insn.i[0] = bfd_getb32 ((unsigned char *) where);
if (6 <= fixp->fx_size)
relocs. In fact, we support *zero* operand relocations ...
Why? Because we are not expecting the compiler to generate
any operands that need relocation. Due to the 12-bit naturew of
- i370 addressing, this would be unusual. */
+ i370 addressing, this would be unusual. */
#if 0
if ((operand->flags & I370_OPERAND_RELATIVE) != 0
&& operand->bits == 12
/* tc-i960.c - All the i80960-specific stuff
- Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 1999
+ Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
Free Software Foundation, Inc.
This file is part of GAS.
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
-/* See comment on md_parse_option for 80960-specific invocation options. */
+/* See comment on md_parse_option for 80960-specific invocation options. */
/* There are 4 different lengths of (potentially) symbol-based displacements
in the 80960 instruction set, each of which could require address fix-ups
#NO_APP at the beginning of its output.
*/
-/* Also note that comments started like this one will always work. */
+/* Also note that comments started like this one will always work. */
const char line_comment_chars[] = "";
*/
const char FLT_CHARS[] = "fFdDtT";
-
/* Table used by base assembler to relax addresses based on varying length
instructions. The fields are:
1) most positive reach of this state,
#define adds(e) e.X_add_symbol
#define offs(e) e.X_add_number
-
/* Branch-prediction bits for CTRL/COBR format opcodes */
#define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
#define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
#define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
-
/* Some instruction opcodes that we need explicitly */
#define BE 0x12000000
#define BG 0x11000000
#define CALLS 0x66003800
#define RET 0x0a000000
-
-/* These masks are used to build up a set of MEMB mode bits. */
+/* These masks are used to build up a set of MEMB mode bits. */
#define A_BIT 0x0400
#define I_BIT 0x0800
#define MEMB_BIT 0x1000
#define D_BIT 0x2000
-
/* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
used). */
#define MEMA_ABASE 0x2000
memS;
-
/* The two pieces of info we need to generate a register operand */
struct regop
{
int n; /* Register number or literal value */
};
-
/* Number and assembler mnemonic for all registers that can appear in
operands. */
static const struct
{ NULL, 0 }, /* END OF LIST */
};
-
/* Hash tables */
static struct hash_control *op_hash; /* Opcode mnemonics */
static struct hash_control *reg_hash; /* Register name hash table */
static struct hash_control *areg_hash; /* Abase register hash table */
-
/* Architecture for which we are assembling */
#define ARCH_ANY 0 /* Default: no architecture checking done */
#define ARCH_KA 1
* instructions.
*/
-
/* BRANCH-PREDICTION INSTRUMENTATION
The following supports generation of branch-prediction instrumentation
const char *bp_error_msg = _("branch prediction invalid on this opcode");
-
/* Parse instruction into opcode and operands */
memset (args, '\0', sizeof (args));
n_ops = i_scan (textP, args);
}
}
-
-
/* Check for branch-prediction suffix on opcode mnemonic, strip it off */
n = strlen (args[0]) - 1;
branch_predict = 0;
return retval;
}
-
#define MAX_LITTLENUMS 6
#define LNUM_SIZE sizeof(LITTLENUM_TYPE)
return 0;
}
-
/*****************************************************************************
md_number_to_imm
md_number_to_chars (buf, val, n);
}
-
/*****************************************************************************
md_number_to_disp
A table of all such "Labels" is also generated.
-
-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
Select the 80960 architecture. Instructions or features not
supported by the selected architecture cause fatal errors.
instr |= (regop.n << 14) | regop.special;
}
-
if (n < 3)
{
emit (instr);
}
} /* cobr_fmt() */
-
/*****************************************************************************
ctrl_fmt: generate a CTRL-format instruction
* how often the branch is taken
*/
-
if (num_ops == 0)
{
emit (opcode); /* Output opcode */
}
-
/*****************************************************************************
emit: output instruction binary
return toP;
}
-
/*****************************************************************************
get_args: break individual arguments out of comma-separated list
return n;
}
-
/*****************************************************************************
get_cdisp: handle displacement for a COBR or CTRL instruction.
}
}
-
/*****************************************************************************
get_ispec: parse a memory operand for an index specification
return (rP == NULL) ? -1 : *rP;
}
-
/*****************************************************************************
i_scan: perform lexical scan of ascii assembler instruction.
*************************************************************************** */
static int
i_scan (iP, args)
- /* Pointer to ascii instruction; MUCKED BY US. */
+ /* Pointer to ascii instruction; MUCKED BY US. */
register char *iP;
/* Output arg: pointers to opcode and operands placed here. MUST
ACCOMMODATE 4 ENTRIES. */
return (get_args (iP, args));
} /* i_scan() */
-
/*****************************************************************************
mem_fmt: generate a MEMA- or MEMB-format instruction
memset (&instr, '\0', sizeof (memS));
instr.opcode = oP->opcode;
- /* Process operands. */
+ /* Process operands. */
for (i = 1; i <= oP->num_ops; i++)
{
opdesc = oP->operand[i - 1];
}
} /* memfmt() */
-
/*****************************************************************************
mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
md_number_to_chars (opcodeP, opcode, 4);
} /* mema_to_memb() */
-
/*****************************************************************************
parse_expr: parse an expression
}
}
-
/*****************************************************************************
parse_ldcont:
Parse and replace a 'ldconst' pseudo-instruction with an appropriate
static char buf2[5]; /* Literal for second operand */
expressionS e; /* Parsed expression */
-
arg[3] = NULL; /* So we can tell at the end if it got used or not */
parse_expr (arg[1], &e);
16 /* MEM16 */
};
-
iprel_flag = mode = 0;
/* Any index present? */
extern char is_end_of_line[];
- /* Advance input pointer to end of line. */
+ /* Advance input pointer to end of line. */
p = input_line_pointer;
while (!is_end_of_line[(unsigned char) *input_line_pointer])
{
struct regop regop; /* Description of register operand */
int n_ops; /* Number of operands */
-
instr = oP->opcode;
n_ops = oP->num_ops;
emit (instr);
}
-
/*****************************************************************************
relax_cobr:
Replace cobr instruction in a code fragment with equivalent branch and
frag_wane (fragP);
}
-
/*****************************************************************************
reloc_callj: Relocate a 'callj' instruction
/* else Symbol is neither a sysproc nor a leafproc */
}
-
/*****************************************************************************
s_leafproc: process .leafproc pseudo-op
return;
} /* Check number of arguments */
- /* Find or create symbol for 'call' entry point. */
+ /* Find or create symbol for 'call' entry point. */
callP = symbol_find_or_make (args[1]);
if (TC_S_IS_CALLNAME (callP))
} /* if only one arg, or the args are the same */
}
-
/*
s_sysproc: process .sysproc pseudo-op
return;
} /* bad arg count */
- /* Parse "entry_num" argument and check it for validity. */
+ /* Parse "entry_num" argument and check it for validity. */
parse_expr (args[2], &exp);
if (exp.X_op != O_constant
|| (offs (exp) < 0)
TC_S_FORCE_TO_SYSPROC (symP);
}
-
/*****************************************************************************
shift_ok:
Determine if a "shlo" instruction can be used to implement a "ldconst".
return shift;
}
-
/* syntax: issue syntax error */
static void
as_bad (_("syntax error"));
} /* syntax() */
-
/* targ_has_sfr:
Return TRUE iff the target architecture supports the specified
}
}
-
/* targ_has_iclass:
Return TRUE iff the target architecture supports the indicated
demand_empty_rest_of_line ();
}
-/* We have no need to default values of symbols. */
+/* We have no need to default values of symbols. */
/* ARGSUSED */
symbolS *
/* Exactly what point is a PC-relative offset relative TO?
On the i960, they're relative to the address of the instruction,
- which we have set up as the address of the fixup too. */
+ which we have set up as the address of the fixup too. */
long
md_pcrel_from (fixP)
fixS *fixP;
ri.r_index = S_GET_TYPE (symbolP);
}
- /* Output the relocation information in machine-dependent form. */
+ /* Output the relocation information in machine-dependent form. */
md_ri_to_chars (where, &ri);
}
if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP))
{
/* Relocation should be done via the associated 'bal'
- entry point symbol. */
+ entry point symbol. */
if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP)))
{
displacement and are only to be used for local branches:
flag as error, don't generate relocation. */
as_bad (_("can't use COBR format with external label"));
- fixP->fx_addsy = NULL; /* No relocations please. */
+ fixP->fx_addsy = NULL; /* No relocations please. */
return 1;
}
}
.line and .file directives will appear in the pre-processed output */
/* Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
- #NO_APP at the beginning of its output. */
-/* Also note that comments like this one will always work. */
+ #NO_APP at the beginning of its output. */
+/* Also note that comments like this one will always work. */
const char line_comment_chars[] = "#*";
const char line_separator_chars[] = ";";
/* Are we trying to generate PIC code? If so, absolute references
ought to be made into linkage table references or pc-relative
- references. Not implemented. For ELF there are other means
+ references. Not implemented. For ELF there are other means
to denote pic relocations. */
int flag_want_pic;
0
};
static const enum m68k_register mcf_control_regs[] = {
- CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
+ CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
RAMBAR0, RAMBAR1, MBAR,
0
};
on the 68000. The 68000 doesn't support long branches with branchs */
/* This table desribes how you change sizes for the various types of variable
- size expressions. This version only supports two kinds. */
+ size expressions. This version only supports two kinds. */
/* Note that calls to frag_var need to specify the maximum expansion
needed; this is currently 10 bytes for DBCC. */
{0, 0, 0}
};
-
/* The mote pseudo ops are put into the opcode table, since they
don't start with a . they look like opcodes to gas.
*/
tc_m68k_fix_adjustable (fixP)
fixS *fixP;
{
- /* Prevent all adjustments to global symbols. */
+ /* Prevent all adjustments to global symbols. */
if (S_IS_EXTERNAL (fixP->fx_addsy)
|| S_IS_WEAK (fixP->fx_addsy))
return 0;
#define relaxable_symbol(symbol) 1
#endif
-
+
/* Handle of the OPCODE hash table. NULL means any use before
m68k_ip_begin() will crash. */
static struct hash_control *op_hash;
instring++; /* skip leading whitespace */
/* Scan up to end of operation-code, which MUST end in end-of-string
- or exactly 1 space. */
+ or exactly 1 space. */
pdot = 0;
for (p = instring; *p != '\0'; p++)
{
for (losing = 0;;)
{
/* If we didn't get the right number of ops, or we have no
- common model with this pattern then reject this pattern. */
+ common model with this pattern then reject this pattern. */
ok_arch |= opcode->m_arch;
if (opsfound != opcode->m_opnum
&& opP->reg != BC))
{
losing++;
- } /* not a cache specifier. */
+ } /* not a cache specifier. */
break;
case '_':
losing++;
/* FIXME: kludge instead of fixing parser:
upper/lower registers are *not* CONTROL
- registers, but ordinary ones. */
+ registers, but ordinary ones. */
if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
|| (opP->reg >= DATA0U && opP->reg <= DATA7U))
opP->mode = DREG;
if (!losing)
{
break;
- } /* got it. */
+ } /* got it. */
opcode = opcode->m_next;
&& m68k_index_width_default == SIZE_LONG))
nextword |= 0x800;
- if ((opP->index.scale != 1
+ if ((opP->index.scale != 1
&& cpu_of_arch (current_architecture) < m68020)
- || (opP->index.scale == 8
+ || (opP->index.scale == 8
&& arch_coldfire_p (current_architecture)))
{
opP->error =
install_operand (s[1], tmpreg);
break;
#ifndef NO_68851
- /* JF: These are out of order, I fear. */
+ /* JF: These are out of order, I fear. */
case 'f':
switch (opP->reg)
{
}
/* By the time whe get here (FINALLY) the_ins contains the complete
- instruction, ready to be emitted. . . */
+ instruction, ready to be emitted. . . */
}
static int
{ "za6", ZADDR6 },
{ "za7", ZADDR7 },
- /* Upper and lower data and address registers, used by macw and msacw. */
+ /* Upper and lower data and address registers, used by macw and msacw. */
{ "d0l", DATA0L },
{ "d1l", DATA1L },
{ "d2l", DATA2L },
{
ins = &m68k_opcodes[i];
/* We *could* ignore insns that don't match our arch here
- but just leaving them out of the hash. */
+ but just leaving them out of the hash. */
slak->m_operands = ins->args;
slak->m_opnum = strlen (slak->m_operands) / 2;
slak->m_arch = ins->arch;
/* Address in gas core of the place to store the displacement. */
/* This convinces the native rs6000 compiler to generate the code we
- want. */
+ want. */
register char *buffer_address = fragP->fr_literal;
buffer_address += fragP->fr_fix;
/* end ibm compiler workaround */
{
if (flag_keep_pcrel)
as_bad (_("long branch not supported"));
-
+
if (fragP->fr_opcode[0] == 0x61)
/* BSR */
{
{
/* This should never happen, because if it's a conditional
branch and we are on a 68000, BCC68000 should have been
- picked instead of ABRANCH. */
+ picked instead of ABRANCH. */
abort ();
}
}
/* change bcc into b!cc/jmp absl long */
if (flag_keep_pcrel)
as_bad (_("long branch not supported"));
-
+
fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
/* JF: these used to be fr_opcode[2,3], but they may be in a
different frag, in which case refering to them is a no-no.
- Only fr_opcode[0,1] are guaranteed to work. */
+ Only fr_opcode[0,1] are guaranteed to work. */
*buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
*buffer_address++ = (char) 0xf9;
fragP->fr_fix += 2; /* account for jmp instruction */
{
/* This should never happen, because if it's a conditional
branch and we are on a 68000, BCC68000 should have been
- picked instead of ABRANCH. */
+ picked instead of ABRANCH. */
abort ();
}
}
else
{
/* Change dbcc into dbcc/bral. */
- /* JF: these used to be fr_opcode[2-4], which is wrong. */
+ /* JF: these used to be fr_opcode[2-4], which is wrong. */
buffer_address[0] = 0x00; /* branch offset = 4 */
buffer_address[1] = 0x04;
- buffer_address[2] = 0x60; /* put in bra pc + ... */
+ buffer_address[2] = 0x60; /* put in bra pc + ... */
/* JF: these were fr_opcode[5-7] */
buffer_address[3] = 0x06; /* Plus 6 */
if (HAVE_LONG_BRANCH (current_architecture))
bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
nibble as nuthin. (on Sun 3 at least) */
/* Translate the internal relocation information into target-specific
- format. */
+ format. */
#ifdef comment
void
md_ri_to_chars (the_bytes, ri)
temp = 1; /* JF should be 2? */
temp_fill = get_absolute_expression ();
- if (!need_pass_2) /* Never make frag if expect extra pass. */
+ if (!need_pass_2) /* Never make frag if expect extra pass. */
frag_align (temp, (int) temp_fill, 0);
demand_empty_rest_of_line ();
record_alignment (now_seg, temp);
cc = reverse_mri_condition (cc);
truelab = falselab;
}
-
+
if (leftstart != NULL)
{
buf = (char *) xmalloc (20
mri_assemble (buf);
free (buf);
}
-
+
buf = (char *) xmalloc (20 + strlen (truelab));
s = buf;
*s++ = 'b';
/* Exactly what point is a PC-relative offset relative TO?
On the 68k, it is relative to the address of the first extension
word. The difference between the addresses of the offset and the
- first extension word is stored in fx_pcrel_adjust. */
+ first extension word is stored in fx_pcrel_adjust. */
long
md_pcrel_from (fixP)
fixS *fixP;
projects / external / binutils.git / commitdiff