ARM: OMAP4: Add L2 Cache Controller in Device Tree
authorSantosh Shilimkar <santosh.shilimkar@ti.com>
Wed, 4 Jul 2012 12:27:34 +0000 (17:57 +0530)
committerBenoit Cousson <b-cousson@ti.com>
Fri, 7 Sep 2012 17:18:41 +0000 (19:18 +0200)
Provide PL310 Level 2 Cache Controller Device Tree
support for OMAP4 based devices.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
arch/arm/boot/dts/omap4.dtsi
arch/arm/mach-omap2/omap4-common.c

index c7dc11f..cb18d2a 100644 (file)
        cpus {
                cpu@0 {
                        compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
                };
                cpu@1 {
                        compatible = "arm,cortex-a9";
+                       next-level-cache = <&L2>;
                };
        };
 
+       L2: l2-cache-controller@48242000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x48242000 0x1000>;
+               cache-unified;
+               cache-level = <2>;
+       };
+
        /*
         * The soc node represents the soc top level view. It is uses for IPs
         * that are not memory mapped in the MPU view or for the MPU itself.
index c29dee9..6f95992 100644 (file)
@@ -16,6 +16,7 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/memblock.h>
+#include <linux/of.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -171,7 +172,10 @@ static int __init omap_l2_cache_init(void)
        /* Enable PL310 L2 Cache controller */
        omap_smc1(0x102, 0x1);
 
-       l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+       if (of_have_populated_dt())
+               l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+       else
+               l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
 
        /*
         * Override default outer_cache.disable with a OMAP4