#include "sysbus.h"
-/* Configuration for arm_gic.c:
- * how to ID current CPU
- */
-static inline int gic_get_current_cpu(void)
-{
- return cpu_single_env->cpu_index;
-}
-
#include "arm_gic.c"
/* A15MP private memory region. */
#include "sysbus.h"
-/* Configuration for arm_gic.c:
- * how to ID current CPU
- */
-static inline int
-gic_get_current_cpu(void)
-{
- return cpu_single_env->cpu_index;
-}
-
#include "arm_gic.c"
/* A9MP private memory region. */
uint32_t num_irq;
} gic_state;
+static inline int gic_get_current_cpu(gic_state *s)
+{
+#if NCPU > 1
+ if (s->num_cpu > 1) {
+ return cpu_single_env->cpu_index;
+ }
+#endif
+ return 0;
+}
+
/* TODO: Many places that call this routine could be optimized. */
/* Update interrupt status after enabled or pending bits have been changed. */
static void gic_update(gic_state *s)
int cm;
int mask;
- cpu = gic_get_current_cpu();
+ cpu = gic_get_current_cpu(s);
cm = 1 << cpu;
if (offset < 0x100) {
#ifndef NVIC
int i;
int cpu;
- cpu = gic_get_current_cpu();
+ cpu = gic_get_current_cpu(s);
if (offset < 0x100) {
#ifdef NVIC
goto bad_reg;
int irq;
int mask;
- cpu = gic_get_current_cpu();
+ cpu = gic_get_current_cpu(s);
irq = value & 0x3ff;
switch ((value >> 24) & 3) {
case 0:
unsigned size)
{
gic_state *s = (gic_state *)opaque;
- return gic_cpu_read(s, gic_get_current_cpu(), addr);
+ return gic_cpu_read(s, gic_get_current_cpu(s), addr);
}
static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
gic_state *s = (gic_state *)opaque;
- gic_cpu_write(s, gic_get_current_cpu(), addr, value);
+ gic_cpu_write(s, gic_get_current_cpu(s), addr, value);
}
/* Wrappers to read/write the GIC CPU interface for a specific CPU.
#define NVIC 1
-/* Only a single "CPU" interface is present. */
-static inline int
-gic_get_current_cpu(void)
-{
- return 0;
-}
-
static uint32_t nvic_readl(void *opaque, uint32_t offset);
static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);