}
}
+void dcn2_get_clock(struct clk_mgr *clk_mgr,
+ struct dc_state *context,
+ enum dc_clock_type clock_type,
+ struct dc_clock_config *clock_cfg)
+{
+
+ if (clock_type == DC_CLOCK_TYPE_DISPCLK) {
+ clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
+ clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
+ clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
+ clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
+ }
+ if (clock_type == DC_CLOCK_TYPE_DPPCLK) {
+ clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
+ clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
+ clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
+ clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
+ }
+}
+
static struct clk_mgr_funcs dcn2_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.update_clocks = dcn2_update_clocks,
.init_clocks = dcn2_init_clocks,
- .enable_pme_wa = dcn2_enable_pme_wa
+ .enable_pme_wa = dcn2_enable_pme_wa,
+ .get_clock = dcn2_get_clock,
};
uint32_t dentist_get_did_from_divider(int divider);
+void dcn2_get_clock(struct clk_mgr *clk_mgr,
+ struct dc_state *context,
+ enum dc_clock_type clock_type,
+ struct dc_clock_config *clock_cfg);
+
#endif //__DCN20_CLK_MGR_H__
info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
}
+enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
+{
+ if (dc->hwss.set_clock)
+ return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
+ return DC_ERROR_UNEXPECTED;
+}
+void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
+{
+ if (dc->hwss.get_clock)
+ dc->hwss.get_clock(dc, clock_type, clock_cfg);
+}
struct dc_clocks {
int dispclk_khz;
int max_supported_dppclk_khz;
+ int max_supported_dispclk_khz;
int dppclk_khz;
+ int bw_dppclk_khz; /*a copy of dppclk_khz*/
+ int bw_dispclk_khz;
int dcfclk_khz;
int socclk_khz;
int dcfclk_deep_sleep_khz;
bool dc_is_dmcu_initialized(struct dc *dc);
+enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
+void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
/*******************************************************************************
* DSC Interfaces
unsigned int phyClock;
};
+
+enum dc_clock_type {
+ DC_CLOCK_TYPE_DISPCLK = 0,
+ DC_CLOCK_TYPE_DPPCLK = 1,
+};
+
+struct dc_clock_config {
+ uint32_t max_clock_khz;
+ uint32_t min_clock_khz;
+ uint32_t bw_requirequired_clock_khz;
+ uint32_t current_clock_khz;/*current clock in use*/
+};
+
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
/* DSC DPCD capabilities */
union dsc_slice_caps1 {
sdp_message_size);
}
}
+static enum dc_status dcn10_set_clock(struct dc *dc,
+ enum dc_clock_type clock_type,
+ uint32_t clk_khz,
+ uint32_t stepping)
+{
+ struct dc_state *context = dc->current_state;
+ struct dc_clock_config clock_cfg = {0};
+ struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;
+
+ if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
+ dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
+ context, clock_type, &clock_cfg);
+
+ if (!dc->clk_mgr->funcs->get_clock)
+ return DC_FAIL_UNSUPPORTED_1;
+
+ if (clk_khz > clock_cfg.max_clock_khz)
+ return DC_FAIL_CLK_EXCEED_MAX;
+
+ if (clk_khz < clock_cfg.min_clock_khz)
+ return DC_FAIL_CLK_BELOW_MIN;
+
+ if (clk_khz < clock_cfg.bw_requirequired_clock_khz)
+ return DC_FAIL_CLK_BELOW_CFG_REQUIRED;
+
+ /*update internal request clock for update clock use*/
+ if (clock_type == DC_CLOCK_TYPE_DISPCLK)
+ current_clocks->dispclk_khz = clk_khz;
+ else if (clock_type == DC_CLOCK_TYPE_DPPCLK)
+ current_clocks->dppclk_khz = clk_khz;
+ else
+ return DC_ERROR_UNEXPECTED;
+
+ if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
+ dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
+ context, true);
+ return DC_OK;
+
+}
+
+static void dcn10_get_clock(struct dc *dc,
+ enum dc_clock_type clock_type,
+ struct dc_clock_config *clock_cfg)
+{
+ struct dc_state *context = dc->current_state;
+
+ if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
+ dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
+
+}
static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = program_gamut_remap,
.enable_stream_gating = NULL,
.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
- .did_underflow_occur = dcn10_did_underflow_occur
+ .set_clock = dcn10_set_clock,
+ .get_clock = dcn10_get_clock,
};
context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
pipe_idx++;
}
+ /*save a original dppclock copy*/
+ context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
+ context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
+ context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz*1000;
+ context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz*1000;
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
DC_NO_DSC_RESOURCE = 17,
#endif
DC_FAIL_UNSUPPORTED_1 = 18,
+ DC_FAIL_CLK_EXCEED_MAX = 21,
+ DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/
+ DC_FAIL_CLK_BELOW_CFG_REQUIRED = 23, /*THIS IS hard_min in PPLIB*/
DC_ERROR_UNEXPECTED = -1
};
#include "dc.h"
+#define DCN_MINIMUM_DISPCLK_Khz 100000
+#define DCN_MINIMUM_DPPCLK_Khz 100000
+
/* Public interfaces */
struct clk_states {
void (*init_clocks)(struct clk_mgr *clk_mgr);
void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
+ void (*get_clock)(struct clk_mgr *clk_mgr,
+ struct dc_state *context,
+ enum dc_clock_type clock_type,
+ struct dc_clock_config *clock_cfg);
};
struct clk_mgr {
void (*disable_writeback)(struct dc *dc,
unsigned int dwb_pipe_inst);
#endif
+ enum dc_status (*set_clock)(struct dc *dc,
+ enum dc_clock_type clock_type,
+ uint32_t clk_khz,
+ uint32_t stepping);
+
+ void (*get_clock)(struct dc *dc,
+ enum dc_clock_type clock_type,
+ struct dc_clock_config *clock_cfg);
+
};
void color_space_to_black_color(