omap4: sdram init changes for omap4460

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 1234a7e..487ec42 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -151,22 +151,13 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
        writel(regs->zq_config, &emif->emif_zq_config);
        writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
        writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
-       /*
-        * Workaround:
-        * In a specific situation, the OCP interface between the DMM and
-        * EMIF may hang.
-        * 1. A TILER port is used to perform 2D burst writes of
-        *       width 1 and height 8
-        * 2. ELLAn port is used to perform reads
-        * 3. All accesses are routed to the same EMIF controller
-        *
-        * Work around to avoid this issue REG_SYS_THRESH_MAX value should
-        * be kept higher than default 0x7. As per recommondation 0x0A will
-        * be used for better performance with REG_LL_THRESH_MAX = 0x00
-        */
-       if (omap_revision() == OMAP4430_ES1_0) {
-               writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00,
-                      &emif->emif_l3_config);
+
+       if (omap_revision() >= OMAP4460_ES1_0) {
+               writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+                       &emif->emif_l3_config);
+       } else {
+               writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
+                       &emif->emif_l3_config);
        }
 }
 
@@ -504,7 +495,7 @@ static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 {
        u32 idle = 0, val = 0;
        if (volt_ramp)
-               val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 + 1;
+               val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
        else
                /*Maximum value in normal conditions - suggested by hw team */
                val = 0x1FF;
@@ -1237,6 +1228,20 @@ static void dmm_init(u32 base)
                &hw_lisa_map_regs->dmm_lisa_map_1);
        writel(lisa_map_regs->dmm_lisa_map_0,
                &hw_lisa_map_regs->dmm_lisa_map_0);
+
+       if (omap_revision() >= OMAP4460_ES1_0) {
+               hw_lisa_map_regs =
+                   (struct dmm_lisa_map_regs *)OMAP44XX_MA_LISA_MAP_BASE;
+
+               writel(lisa_map_regs->dmm_lisa_map_3,
+                       &hw_lisa_map_regs->dmm_lisa_map_3);
+               writel(lisa_map_regs->dmm_lisa_map_2,
+                       &hw_lisa_map_regs->dmm_lisa_map_2);
+               writel(lisa_map_regs->dmm_lisa_map_1,
+                       &hw_lisa_map_regs->dmm_lisa_map_1);
+               writel(lisa_map_regs->dmm_lisa_map_0,
+                       &hw_lisa_map_regs->dmm_lisa_map_0);
+       }
 }
 
 /*

diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index a167508..37ad1fd 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -248,6 +248,8 @@
 /* OCP_CONFIG */
 #define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT              24
 #define OMAP44XX_REG_SYS_THRESH_MAX_MASK               (0xf << 24)
+#define OMAP44XX_REG_MPU_THRESH_MAX_SHIFT              20
+#define OMAP44XX_REG_MPU_THRESH_MAX_MASK               (0xf << 20)
 #define OMAP44XX_REG_LL_THRESH_MAX_SHIFT               16
 #define OMAP44XX_REG_LL_THRESH_MAX_MASK                        (0xf << 16)
 #define OMAP44XX_REG_PR_OLD_COUNT_SHIFT                        0
@@ -472,6 +474,9 @@
 /* DMM */
 #define OMAP44XX_DMM_LISA_MAP_BASE     0x4E000040
 
+/* Memory Adapter (4460 onwards) */
+#define OMAP44XX_MA_LISA_MAP_BASE              0x482AF040
+
 /* DMM_LISA_MAP */
 #define OMAP44XX_SYS_ADDR_SHIFT                24
 #define OMAP44XX_SYS_ADDR_MASK         (0xff << 24)
@@ -774,8 +779,9 @@ struct control_lpddr2io_regs {
        ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
                        & OMAP44XX_REG_PD_TIM_SHDW_MASK))
 
-/* EMIF_L3_CONFIG register value for ES1*/
-#define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00  0x0A0000FF
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0   0x0A300000
 /*
  * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
  * All these fields have magic values dependent on frequency and