Add clock driver about sys, stg and aon clock for JH7110.
Clock references refer to include/dt-bindings/clock/starfive-jh7110-clkgen.h
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
/dts-v1/;
#include <dt-bindings/reset/starfive-jh7110.h>
#include "starfive_jh7110_clk.dtsi"
+#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
/ {
#address-cells = <2>;
riscv,ndev = <136>;
};
+ clkgen: clock-controller {
+ compatible = "starfive,jh7110-clkgen";
+ reg = <0x0 0x13020000 0x0 0x10000>,
+ <0x0 0x10230000 0x0 0x10000>,
+ <0x0 0x17000000 0x0 0x10000>;
+ reg-names = "sys", "stg", "aon";
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>,
+ <&jtag_tck_inner>, <&bist_apb>,
+ <&stg_apb>, <&clk_rtc>,
+ <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
+ "i2stx_bclk_ext", "i2stx_lrck_ext",
+ "i2srx_bclk_ext", "i2srx_lrck_ext",
+ "tdm_ext", "mclk_ext",
+ "jtag_tck_inner", "bist_apb",
+ "stg_apb", "clk_rtc",
+ "gmac0_rmii_refin", "gmac0_rgmii_rxin";
+ #clock-cells = <1>;
+ status = "okay";
+ };
+
+ clkvout: clock-controller@295C0000 {
+ compatible = "starfive,jh7110-clk-vout";
+ reg = <0x0 0x295C0000 0x0 0x10000>;
+ reg-names = "vout";
+ clocks = <&hdmitx0_pixelclk>,
+ <&mipitx_dphy_rxesc>,
+ <&mipitx_dphy_txbytehs>;
+ clock-names = "hdmitx0_pixelclk",
+ "mipitx_dphy_rxesc",
+ "mipitx_dphy_txbytehs";
+ #clock-cells = <1>;
+ status = "disabled";
+ };
+
+ clkisp: clock-controller@19810000 {
+ compatible = "starfive,jh7110-clk-isp";
+ reg = <0x0 0x19810000 0x0 0x10000>;
+ reg-names = "isp";
+ #clock-cells = <1>;
+ status = "disabled";
+ };
+
timer: timer@13050000 {
compatible = "starfive,si5-timers";
reg = <0x0 0x13050000 0x0 0x10000>;
reg = <0x0 0x10000000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
- clocks = <&oscclk>, <&apb0clk>;
+ clocks = <&clkgen JH7110_UART0_CLK_CORE>,
+ <&clkgen JH7110_UART0_CLK_APB>;
clock-names = "baudclk", "apb_pclk";
status = "okay";
};
clock-frequency = <24000000>;
};
pwmclk: pwmclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- };
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ };
audioclk: audioclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12288000>;
- };
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12288000>;
+ };
clk_ext_camera: clk-ext-camera {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
canclk: canclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- };
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+
+ /* clock tree external clocks */
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ gmac1_rmii_refin: gmac1_rmii_refin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ gmac1_rgmii_rxin: gmac1_rgmii_rxin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ i2stx_bclk_ext: i2stx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+
+ i2stx_lrck_ext: i2stx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <192000>;
+ };
+
+ i2srx_bclk_ext: i2srx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+
+ i2srx_lrck_ext: i2srx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <192000>;
+ };
+
+ tdm_ext: tdm_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <49152000>;
+ };
+
+ mclk_ext: mclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <49152000>;
+ };
+
+ jtag_tck_inner: jtag_tck_inner {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ bist_apb: bist_apb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ stg_apb: stg_apb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <51200000>;
+ };
+
+ gmac0_rmii_refin: gmac0_rmii_refin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk_rtc: clk_rtc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ hdmitx0_pixelclk: hdmitx0_pixelclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <297000000>;
+ };
+
+ mipitx_dphy_rxesc: mipitx_dphy_rxesc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <10000000>;
+ };
+
+ mipitx_dphy_txbytehs: mipitx_dphy_txbytehs {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <297000000>;
+ };
+
+ /* external clocks end */
};
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/socfpga/Kconfig"
source "drivers/clk/sprd/Kconfig"
+source "drivers/clk/starfive/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sunxi-ng/Kconfig"
source "drivers/clk/tegra/Kconfig"
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_ARCH_STI) += st/
+obj-$(CONFIG_SOC_STARFIVE_JH7110) += starfive/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_SUNXI_CCU) += sunxi-ng/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_STARFIVE_JH7110
+ bool "StarFive JH7110 clock support"
+ depends on SOC_STARFIVE_JH7110 || COMPILE_TEST
+ default y if SOC_STARFIVE_JH7110
+ help
+ Say yes here to support the clock controller on the StarFive
+ JH7110 SoC.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# StarFive Clock
+obj-$(CONFIG_CLK_STARFIVE_JH7110) += clk-starfive-jh7110-gen.o \
+ clk-starfive-jh7110-sys.o \
+ clk-starfive-jh7110-stg.o \
+ clk-starfive-jh7110-aon.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 aon Clock Generator Driver
+ *
+ * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+#include "clk-starfive-jh7110.h"
+
+static const struct jh7110_clk_data jh7110_clk_aon_data[] __initconst = {
+ //source
+ JH7110__DIV(JH7110_OSC_DIV4, "osc_div4", 4, JH7110_OSC),
+ JH7110__MUX(JH7110_AON_APB_FUNC, "aon_apb_func", 2,
+ JH7110_OSC_DIV4,
+ JH7110_OSC),
+ //gmac5
+ JH7110_GATE(JH7110_U0_GMAC5_CLK_AHB,
+ "u0_dw_gmac5_axi64_clk_ahb", 0, JH7110_AON_AHB),
+ JH7110_GATE(JH7110_U0_GMAC5_CLK_AXI,
+ "u0_dw_gmac5_axi64_clk_axi", 0, JH7110_AON_AHB),
+ JH7110__DIV(JH7110_GMAC0_RMII_RTX,
+ "gmac0_rmii_rtx", 30, JH7110_GMAC0_RMII_REFIN),
+ JH7110_GMUX(JH7110_U0_GMAC5_CLK_TX,
+ "u0_dw_gmac5_axi64_clk_tx", 0, 2,
+ JH7110_GMAC0_GTXCLK,
+ JH7110_GMAC0_RMII_RTX),
+ JH7110__INV(JH7110_U0_GMAC5_CLK_TX_INV,
+ "u0_dw_gmac5_axi64_clk_tx_inv",
+ JH7110_U0_GMAC5_CLK_TX),
+ JH7110__MUX(JH7110_U0_GMAC5_CLK_RX,
+ "u0_dw_gmac5_axi64_clk_rx", 2,
+ JH7110_GMAC0_RGMII_RXIN,
+ JH7110_GMAC0_RMII_RTX),
+ JH7110__INV(JH7110_U0_GMAC5_CLK_RX_INV,
+ "u0_dw_gmac5_axi64_clk_rx_inv",
+ JH7110_U0_GMAC5_CLK_RX),
+ //otpc
+ JH7110_GATE(JH7110_OTPC_CLK_APB,
+ "u0_otpc_clk_apb", 0, JH7110_AON_APB),
+ //rtc
+ JH7110_GATE(JH7110_RTC_HMS_CLK_APB,
+ "u0_rtc_hms_clk_apb", 0, JH7110_AON_APB),
+ JH7110__DIV(JH7110_RTC_INTERNAL,
+ "rtc_internal", 1022, JH7110_OSC),
+ JH7110__MUX(JH7110_RTC_HMS_CLK_OSC32K,
+ "u0_rtc_hms_clk_osc32k", 2,
+ JH7110_CLK_RTC,
+ JH7110_RTC_INTERNAL),
+ JH7110_GATE(JH7110_RTC_HMS_CLK_CAL,
+ "u0_rtc_hms_clk_cal", 0, JH7110_OSC),
+};
+
+const int __init clk_starfive_jh7110_aon_init(struct platform_device *pdev,
+ struct jh7110_clk_priv *priv)
+{
+ unsigned int idx;
+ int ret = 0;
+
+ priv->aon_base = devm_platform_ioremap_resource_byname(pdev, "aon");
+ if (IS_ERR(priv->aon_base))
+ return PTR_ERR(priv->aon_base);
+
+ priv->pll[PLL_OF(JH7110_U0_GMAC5_CLK_PTP)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_dw_gmac5_axi64_clk_ptp", "gmac0_ptp", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_U0_GMAC5_CLK_RMII)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_dw_gmac5_axi64_clk_rmii",
+ "gmac0_rmii_refin", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_AON_SYSCON_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_aon_syscon_pclk", "aon_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_AON_IOMUX_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_aon_iomux_pclk", "aon_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_AON_CRG_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_aon_crg_pclk", "aon_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PMU_CLK_APB)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_pmu_clk_apb", "aon_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PMU_CLK_WKUP)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_pmu_clk_wkup", "aon_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_RTC_HMS_CLK_OSC32K_G)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_rtc_hms_clk_osc32k_g",
+ "u0_rtc_hms_clk_osc32k", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_32K_OUT)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "32k_out", "clk_rtc", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_RESET0_CTRL_CLK_SRC)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_reset_ctrl_clk_src", "osc", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PCLK_MUX_FUNC_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_pclk_mux_func_pclk", "aon_apb_func", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PCLK_MUX_BIST_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_pclk_mux_bist_pclk", "bist_apb", 0, 1, 1);
+
+ for (idx = JH7110_CLK_STG_REG_END; idx < JH7110_CLK_REG_END; idx++) {
+ u32 max = jh7110_clk_aon_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_clk_aon_data[idx].name,
+ .ops = starfive_jh7110_clk_ops(max),
+ .parent_data = parents,
+ .num_parents = ((max & JH7110_CLK_MUX_MASK) \
+ >> JH7110_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_clk_aon_data[idx].flags,
+ };
+ struct jh7110_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_clk_aon_data[idx].parents[i];
+
+ if (pidx < JH7110_CLK_REG_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if ((pidx < JH7110_CLK_END) && \
+ (pidx > JH7110_RTC_HMS_CLK_CAL))
+ parents[i].hw = priv->pll[PLL_OF(pidx)];
+ else if (pidx == JH7110_GMAC0_RMII_REFIN)
+ parents[i].fw_name = "gmac0_rmii_refin";
+ else if (pidx == JH7110_GMAC0_RGMII_RXIN)
+ parents[i].fw_name = "gmac0_rgmii_rxin";
+ else if (pidx == JH7110_CLK_RTC)
+ parents[i].fw_name = "clk_rtc";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH7110_CLK_DIV_MASK;
+ clk->reg_flags = JH7110_CLK_AON_FLAG;
+
+ ret = devm_clk_hw_register(priv->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ dev_dbg(&pdev->dev,"starfive JH7110 clk_aon init successfully.");
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Clock Generator Driver
+ *
+ * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+
+#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+#include "clk-starfive-jh7110.h"
+
+static struct jh7110_clk * __init jh7110_clk_from(struct clk_hw *hw)
+{
+ return container_of(hw, struct jh7110_clk, hw);
+}
+
+static struct jh7110_clk_priv *jh7110_priv_from(struct jh7110_clk *clk)
+{
+ return container_of(clk, struct jh7110_clk_priv, reg[clk->idx]);
+}
+
+void __iomem *jh7110_clk_reg_addr_get(struct jh7110_clk *clk)
+{
+ void __iomem *reg;
+ struct jh7110_clk_priv *priv = jh7110_priv_from(clk);
+
+ if (clk->reg_flags == JH7110_CLK_SYS_FLAG)
+ reg = priv->sys_base + 4 * clk->idx;
+ else if (clk->reg_flags == JH7110_CLK_STG_FLAG)
+ reg = priv->stg_base + 4 * (clk->idx - JH7110_CLK_SYS_REG_END);
+ else if (clk->reg_flags == JH7110_CLK_AON_FLAG)
+ reg = priv->aon_base + 4 * (clk->idx - JH7110_CLK_STG_REG_END);
+ else if (clk->reg_flags == JH7110_CLK_VOUT_FLAG)
+ reg = priv->vout_base + 4 * clk->idx;
+ else if (clk->reg_flags == JH7110_CLK_ISP_FLAG)
+ reg = priv->isp_base + 4 * clk->idx;
+
+ return reg;
+}
+
+static u32 jh7110_clk_reg_get(struct jh7110_clk *clk)
+{
+ void __iomem *reg = jh7110_clk_reg_addr_get(clk);
+
+ return readl_relaxed(reg);
+}
+
+static void jh7110_clk_reg_rmw(struct jh7110_clk *clk, u32 mask, u32 value)
+{
+ struct jh7110_clk_priv *priv = jh7110_priv_from(clk);
+ void __iomem *reg = jh7110_clk_reg_addr_get(clk);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->rmw_lock, flags);
+ value |= readl_relaxed(reg) & ~mask;
+ writel_relaxed(value, reg);
+ spin_unlock_irqrestore(&priv->rmw_lock, flags);
+}
+
+static int jh7110_clk_enable(struct clk_hw *hw)
+{
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+
+ jh7110_clk_reg_rmw(clk, JH7110_CLK_ENABLE, JH7110_CLK_ENABLE);
+ return 0;
+}
+
+static void jh7110_clk_disable(struct clk_hw *hw)
+{
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+
+ jh7110_clk_reg_rmw(clk, JH7110_CLK_ENABLE, 0);
+}
+
+static int jh7110_clk_is_enabled(struct clk_hw *hw)
+{
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+
+ return !!(jh7110_clk_reg_get(clk) & JH7110_CLK_ENABLE);
+}
+
+static unsigned long jh7110_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+ u32 div = jh7110_clk_reg_get(clk) & JH7110_CLK_DIV_MASK;
+
+ return div ? parent_rate / div : 0;
+}
+
+static int jh7110_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+ unsigned long parent = req->best_parent_rate;
+ unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
+ unsigned long div = min_t(unsigned long,
+ DIV_ROUND_UP(parent, rate), clk->max_div);
+ unsigned long result = parent / div;
+
+ /*
+ * we want the result clamped by min_rate and max_rate if possible:
+ * case 1: div hits the max divider value, which means it's less than
+ * parent / rate, so the result is greater than rate and min_rate in
+ * particular. we can't do anything about result > max_rate because the
+ * divider doesn't go any further.
+ * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
+ * always lower or equal to rate and max_rate. however the result may
+ * turn out lower than min_rate, but then the next higher rate is fine:
+ * div - 1 = ceil(parent / rate) - 1 < parent / rate
+ * and thus
+ * min_rate <= rate < parent / (div - 1)
+ */
+ if (result < req->min_rate && div > 1)
+ result = parent / (div - 1);
+
+ req->rate = result;
+ return 0;
+}
+
+static int jh7110_clk_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+ unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
+ 1UL, (unsigned long)clk->max_div);
+
+ jh7110_clk_reg_rmw(clk, JH7110_CLK_DIV_MASK, div);
+ return 0;
+}
+
+static u8 jh7110_clk_get_parent(struct clk_hw *hw)
+{
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+ u32 value = jh7110_clk_reg_get(clk);
+
+ return (value & JH7110_CLK_MUX_MASK) >> JH7110_CLK_MUX_SHIFT;
+}
+
+static int jh7110_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+ u32 value = (u32)index << JH7110_CLK_MUX_SHIFT;
+
+ jh7110_clk_reg_rmw(clk, JH7110_CLK_MUX_MASK, value);
+ return 0;
+}
+
+static int jh7110_clk_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ return clk_mux_determine_rate_flags(hw, req, 0);
+}
+
+static int jh7110_clk_get_phase(struct clk_hw *hw)
+{
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+ u32 value = jh7110_clk_reg_get(clk);
+
+ return (value & JH7110_CLK_INVERT) ? 180 : 0;
+}
+
+static int jh7110_clk_set_phase(struct clk_hw *hw, int degrees)
+{
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+ u32 value;
+
+ if (degrees == 0)
+ value = 0;
+ else if (degrees == 180)
+ value = JH7110_CLK_INVERT;
+ else
+ return -EINVAL;
+
+ jh7110_clk_reg_rmw(clk, JH7110_CLK_INVERT, value);
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void jh7110_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ static const struct debugfs_reg32 jh7110_clk_reg = {
+ .name = "CTRL",
+ .offset = 0,
+ };
+ struct jh7110_clk *clk = jh7110_clk_from(hw);
+ struct jh7110_clk_priv *priv = jh7110_priv_from(clk);
+ struct debugfs_regset32 *regset;
+
+ regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
+ if (!regset)
+ return;
+
+ regset->regs = &jh7110_clk_reg;
+ regset->nregs = 1;
+ regset->base = jh7110_clk_reg_addr_get(clk);
+
+ debugfs_create_regset32("registers", 0400, dentry, regset);
+}
+#else
+#define jh7110_clk_debug_init NULL
+#endif
+
+static const struct clk_ops jh7110_clk_gate_ops = {
+ .enable = jh7110_clk_enable,
+ .disable = jh7110_clk_disable,
+ .is_enabled = jh7110_clk_is_enabled,
+ .debug_init = jh7110_clk_debug_init,
+};
+
+static const struct clk_ops jh7110_clk_div_ops = {
+ .recalc_rate = jh7110_clk_recalc_rate,
+ .determine_rate = jh7110_clk_determine_rate,
+ .set_rate = jh7110_clk_set_rate,
+ .debug_init = jh7110_clk_debug_init,
+};
+
+static const struct clk_ops jh7110_clk_gdiv_ops = {
+ .enable = jh7110_clk_enable,
+ .disable = jh7110_clk_disable,
+ .is_enabled = jh7110_clk_is_enabled,
+ .recalc_rate = jh7110_clk_recalc_rate,
+ .determine_rate = jh7110_clk_determine_rate,
+ .set_rate = jh7110_clk_set_rate,
+ .debug_init = jh7110_clk_debug_init,
+};
+
+static const struct clk_ops jh7110_clk_mux_ops = {
+ .determine_rate = jh7110_clk_mux_determine_rate,
+ .set_parent = jh7110_clk_set_parent,
+ .get_parent = jh7110_clk_get_parent,
+ .debug_init = jh7110_clk_debug_init,
+};
+
+static const struct clk_ops jh7110_clk_gmux_ops = {
+ .enable = jh7110_clk_enable,
+ .disable = jh7110_clk_disable,
+ .is_enabled = jh7110_clk_is_enabled,
+ .determine_rate = jh7110_clk_mux_determine_rate,
+ .set_parent = jh7110_clk_set_parent,
+ .get_parent = jh7110_clk_get_parent,
+ .debug_init = jh7110_clk_debug_init,
+};
+
+static const struct clk_ops jh7110_clk_mdiv_ops = {
+ .recalc_rate = jh7110_clk_recalc_rate,
+ .determine_rate = jh7110_clk_determine_rate,
+ .get_parent = jh7110_clk_get_parent,
+ .set_parent = jh7110_clk_set_parent,
+ .set_rate = jh7110_clk_set_rate,
+ .debug_init = jh7110_clk_debug_init,
+};
+
+static const struct clk_ops jh7110_clk_gmd_ops = {
+ .enable = jh7110_clk_enable,
+ .disable = jh7110_clk_disable,
+ .is_enabled = jh7110_clk_is_enabled,
+ .recalc_rate = jh7110_clk_recalc_rate,
+ .determine_rate = jh7110_clk_determine_rate,
+ .get_parent = jh7110_clk_get_parent,
+ .set_parent = jh7110_clk_set_parent,
+ .set_rate = jh7110_clk_set_rate,
+ .debug_init = jh7110_clk_debug_init,
+};
+
+static const struct clk_ops jh7110_clk_inv_ops = {
+ .get_phase = jh7110_clk_get_phase,
+ .set_phase = jh7110_clk_set_phase,
+ .debug_init = jh7110_clk_debug_init,
+};
+
+const struct clk_ops *starfive_jh7110_clk_ops(u32 max)
+{
+ if (max & JH7110_CLK_DIV_MASK) {
+ if (max & JH7110_CLK_MUX_MASK) {
+ if (max & JH7110_CLK_ENABLE)
+ return &jh7110_clk_gmd_ops;
+ return &jh7110_clk_mdiv_ops;
+ }
+ if (max & JH7110_CLK_ENABLE)
+ return &jh7110_clk_gdiv_ops;
+ return &jh7110_clk_div_ops;
+ }
+
+ if (max & JH7110_CLK_MUX_MASK) {
+ if (max & JH7110_CLK_ENABLE)
+ return &jh7110_clk_gmux_ops;
+ return &jh7110_clk_mux_ops;
+ }
+
+ if (max & JH7110_CLK_ENABLE)
+ return &jh7110_clk_gate_ops;
+
+ return &jh7110_clk_inv_ops;
+}
+EXPORT_SYMBOL_GPL(starfive_jh7110_clk_ops);
+
+static struct clk_hw *jh7110_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh7110_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_PLL0_OUT)
+ return &priv->reg[idx].hw;
+
+ if (idx < JH7110_CLK_END)
+ return priv->pll[PLL_OF(idx)];
+
+ return ERR_PTR(-EINVAL);
+}
+
+
+static int __init clk_starfive_jh7110_probe(struct platform_device *pdev)
+{
+ struct jh7110_clk_priv *priv;
+ int ret = 0;
+
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_PLL0_OUT),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+
+ ret = clk_starfive_jh7110_sys_init(pdev, priv);
+ if (ret)
+ return ret;
+
+ ret = clk_starfive_jh7110_stg_init(pdev, priv);
+ if (ret)
+ return ret;
+
+ ret = clk_starfive_jh7110_aon_init(pdev, priv);
+ if (ret)
+ return ret;
+
+ ret = devm_of_clk_add_hw_provider(priv->dev, jh7110_clk_get, priv);
+ if (ret)
+ return ret;
+
+ dev_info(&pdev->dev,"starfive JH7110 clkgen init successfully.");
+ return 0;
+}
+
+static const struct of_device_id clk_starfive_jh7110_match[] = {
+ {.compatible = "starfive,jh7110-clkgen"},
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_starfive_jh7110_driver = {
+ .driver = {
+ .name = "clk-starfive-jh7110",
+ .of_match_table = clk_starfive_jh7110_match,
+ },
+};
+builtin_platform_driver_probe(clk_starfive_jh7110_driver,
+ clk_starfive_jh7110_probe);
+
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JH7110 sysgen clock driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 stg Clock Generator Driver
+ *
+ * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+#include "clk-starfive-jh7110.h"
+
+static const struct jh7110_clk_data jh7110_clk_stg_data[] __initconst = {
+ //hifi4
+ JH7110_GATE(JH7110_HIFI4_CLK_CORE, "u0_hifi4_clk_core",
+ 0, JH7110_HIFI4_CORE),
+ //usb
+ JH7110_GATE(JH7110_USB0_CLK_USB_APB, "u0_cdn_usb_clk_usb_apb",
+ 0, JH7110_STG_APB),
+ JH7110_GATE(JH7110_USB0_CLK_UTMI_APB, "u0_cdn_usb_clk_utmi_apb",
+ 0, JH7110_STG_APB),
+ JH7110_GATE(JH7110_USB0_CLK_AXI, "u0_cdn_usb_clk_axi",
+ 0, JH7110_STG_AXIAHB),
+ JH7110_GDIV(JH7110_USB0_CLK_LPM, "u0_cdn_usb_clk_lpm",
+ 0, 2, JH7110_OSC),
+ JH7110_GDIV(JH7110_USB0_CLK_STB, "u0_cdn_usb_clk_stb",
+ 0, 4, JH7110_OSC),
+ JH7110_GATE(JH7110_USB0_CLK_APP_125, "u0_cdn_usb_clk_app_125",
+ 0, JH7110_USB_125M),
+ JH7110__DIV(JH7110_USB0_REFCLK, "u0_cdn_usb_refclk", 2, JH7110_OSC),
+ //pci-e
+ JH7110_GATE(JH7110_PCIE0_CLK_AXI_MST0, "u0_plda_pcie_clk_axi_mst0",
+ 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_PCIE0_CLK_APB, "u0_plda_pcie_clk_apb",
+ 0, JH7110_STG_APB),
+ JH7110_GATE(JH7110_PCIE0_CLK_TL, "u0_plda_pcie_clk_tl",
+ 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_PCIE1_CLK_AXI_MST0, "u1_plda_pcie_clk_axi_mst0",
+ 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_PCIE1_CLK_APB, "u1_plda_pcie_clk_apb",
+ 0, JH7110_STG_APB),
+ JH7110_GATE(JH7110_PCIE1_CLK_TL, "u1_plda_pcie_clk_tl",
+ 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_PCIE01_SLV_DEC_MAINCLK, "u0_pcie01_slv_dec_mainclk",
+ 0, JH7110_STG_AXIAHB),
+ //security
+ JH7110_GATE(JH7110_SEC_HCLK, "u0_sec_top_hclk",
+ 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_SEC_MISCAHB_CLK, "u0_sec_top_miscahb_clk",
+ 0, JH7110_STG_AXIAHB),
+ //stg mtrx
+ JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_MAIN, "u0_stg_mtrx_grp0_clk_main",
+ 0, JH7110_CPU_BUS),
+ JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_BUS, "u0_stg_mtrx_grp0_clk_bus",
+ 0, JH7110_NOCSTG_BUS),
+ JH7110_GATE(JH7110_STG_MTRX_GRP0_CLK_STG, "u0_stg_mtrx_grp0_clk_stg",
+ 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_MAIN, "u0_stg_mtrx_grp1_clk_main",
+ 0, JH7110_CPU_BUS),
+ JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_BUS, "u0_stg_mtrx_grp1_clk_bus",
+ 0, JH7110_NOCSTG_BUS),
+ JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_STG, "u0_stg_mtrx_grp1_clk_stg",
+ 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_STG_MTRX_GRP1_CLK_HIFI, "u0_stg_mtrx_grp1_clk_hifi",
+ 0, JH7110_HIFI4_AXI),
+ //e24_rvpi
+ JH7110_GDIV(JH7110_E2_RTC_CLK, "u0_e2_sft7110_rtc_clk",
+ 0, 24, JH7110_OSC),
+ JH7110_GATE(JH7110_E2_CLK_CORE, "u0_e2_sft7110_clk_core",
+ 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_E2_CLK_DBG, "u0_e2_sft7110_clk_dbg",
+ 0, JH7110_STG_AXIAHB),
+ //dw_sgdma1p
+ JH7110_GATE(JH7110_DMA1P_CLK_AXI, "u0_dw_dma1p_8ch_56hs_clk_axi",
+ 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_DMA1P_CLK_AHB, "u0_dw_dma1p_8ch_56hs_clk_ahb",
+ 0, JH7110_STG_AXIAHB),
+};
+
+const int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev,
+ struct jh7110_clk_priv *priv)
+{
+ unsigned int idx;
+ int ret = 0;
+
+ priv->stg_base = devm_platform_ioremap_resource_byname(pdev, "stg");
+ if (IS_ERR(priv->stg_base))
+ return PTR_ERR(priv->stg_base);
+
+ priv->pll[PLL_OF(JH7110_PCIE0_CLK_AXI_SLV0)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_plda_pcie_clk_axi_slv0",
+ "u0_plda_pcie_clk_axi_mst0", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PCIE0_CLK_AXI_SLV)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_plda_pcie_clk_axi_slv",
+ "u0_plda_pcie_clk_axi_mst0", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PCIE0_CLK_OSC)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_plda_pcie_clk_osc", "osc", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PCIE1_CLK_AXI_SLV0)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_plda_pcie_clk_axi_slv0",
+ "u1_plda_pcie_clk_axi_mst0", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PCIE1_CLK_AXI_SLV)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_plda_pcie_clk_axi_slv",
+ "u1_plda_pcie_clk_axi_mst0", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PCIE1_CLK_OSC)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_plda_pcie_clk_osc", "osc", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_E2_IRQ_SYNC_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_e2_sft7110_irq_sync_clk_core",
+ "stg_axiahb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_STG_CRG_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_stg_crg_pclk", "stg_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_STG_SYSCON_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_stg_syscon_pclk", "stg_apb", 0, 1, 1);
+
+ for (idx = JH7110_CLK_SYS_REG_END; idx < JH7110_CLK_STG_REG_END; idx++) {
+ u32 max = jh7110_clk_stg_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_clk_stg_data[idx].name,
+ .ops = starfive_jh7110_clk_ops(max),
+ .parent_data = parents,
+ .num_parents = ((max & JH7110_CLK_MUX_MASK) \
+ >> JH7110_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_clk_stg_data[idx].flags,
+ };
+ struct jh7110_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_clk_stg_data[idx].parents[i];
+
+ if (pidx < JH7110_CLK_STG_REG_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if ((pidx < JH7110_CLK_STG_END) && \
+ (pidx > JH7110_CLK_SYS_END))
+ parents[i].hw = priv->pll[PLL_OF(pidx)];
+ else if (pidx == JH7110_STG_APB)
+ parents[i].fw_name = "stg_apb";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH7110_CLK_DIV_MASK;
+ clk->reg_flags = JH7110_CLK_STG_FLAG;
+
+ ret = devm_clk_hw_register(priv->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ dev_dbg(&pdev->dev,"starfive JH7110 clk_stg init successfully.");
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 sys Clock Generator Driver
+ *
+ * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+#include "clk-starfive-jh7110.h"
+
+static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
+ /*root*/
+ JH7110__MUX(JH7110_CPU_ROOT, "cpu_root", 2,
+ JH7110_OSC,
+ JH7110_PLL0_OUT),
+ JH7110__DIV(JH7110_CPU_CORE, "cpu_core", 7, JH7110_CPU_ROOT),
+ JH7110__DIV(JH7110_CPU_BUS, "cpu_bus", 2, JH7110_CPU_CORE),
+ JH7110__MUX(JH7110_GPU_ROOT, "gpu_root", 2,
+ JH7110_PLL2_OUT,
+ JH7110_PLL1_OUT),
+ JH7110_MDIV(JH7110_PERH_ROOT, "perh_root", 2, 2,
+ JH7110_PLL0_OUT,
+ JH7110_PLL2_OUT),
+ JH7110__MUX(JH7110_BUS_ROOT, "bus_root", 2,
+ JH7110_OSC,
+ JH7110_PLL2_OUT),
+ JH7110__DIV(JH7110_NOCSTG_BUS, "nocstg_bus", 3, JH7110_BUS_ROOT),
+ JH7110__DIV(JH7110_AXI_CFG0, "axi_cfg0", 3, JH7110_BUS_ROOT),
+ JH7110__DIV(JH7110_STG_AXIAHB, "stg_axiahb", 2, JH7110_AXI_CFG0),
+ JH7110_GATE(JH7110_AHB0, "ahb0", 0, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_AHB1, "ahb1", 0, JH7110_STG_AXIAHB),
+ JH7110__DIV(JH7110_APB_BUS_FUNC, "apb_bus_func",
+ 8, JH7110_STG_AXIAHB),
+ JH7110_GATE(JH7110_APB0, "apb0", 0, JH7110_APB_BUS),
+ JH7110__DIV(JH7110_PLL0_DIV2, "pll0_div2", 2, JH7110_PLL0_OUT),
+ JH7110__DIV(JH7110_PLL1_DIV2, "pll1_div2", 2, JH7110_PLL1_OUT),
+ JH7110__DIV(JH7110_PLL2_DIV2, "pll2_div2", 2, JH7110_PLL2_OUT),
+ JH7110__DIV(JH7110_AUDIO_ROOT, "audio_root", 8, JH7110_PLL2_OUT),
+ JH7110__DIV(JH7110_MCLK_INNER, "mclk_inner", 64, JH7110_AUDIO_ROOT),
+ JH7110__MUX(JH7110_MCLK, "mclk", 2,
+ JH7110_MCLK_INNER,
+ JH7110_MCLK_EXT),
+ JH7110_GATE(JH7110_MCLK_OUT, "mclk_out", 0, JH7110_MCLK_INNER),
+ JH7110_MDIV(JH7110_ISP_2X, "isp_2x", 8, 2,
+ JH7110_PLL2_OUT,
+ JH7110_PLL1_OUT),
+ JH7110__DIV(JH7110_ISP_AXI, "isp_axi", 4, JH7110_ISP_2X),
+ JH7110_GDIV(JH7110_GCLK0, "gclk0", 0, 62, JH7110_PLL0_DIV2),
+ JH7110_GDIV(JH7110_GCLK1, "gclk1", 0, 62, JH7110_PLL1_DIV2),
+ JH7110_GDIV(JH7110_GCLK2, "gclk2", 0, 62, JH7110_PLL2_DIV2),
+ /*u0_u7mc_sft7110*/
+ JH7110_GATE(JH7110_U7_CORE_CLK, "u0_u7mc_sft7110_core_clk",
+ 0, JH7110_CPU_CORE),
+ JH7110_GATE(JH7110_U7_CORE_CLK1, "u0_u7mc_sft7110_core_clk1",
+ 0, JH7110_CPU_CORE),
+ JH7110_GATE(JH7110_U7_CORE_CLK2, "u0_u7mc_sft7110_core_clk2",
+ 0, JH7110_CPU_CORE),
+ JH7110_GATE(JH7110_U7_CORE_CLK3, "u0_u7mc_sft7110_core_clk3",
+ 0, JH7110_CPU_CORE),
+ JH7110_GATE(JH7110_U7_CORE_CLK4, "u0_u7mc_sft7110_core_clk4",
+ 0, JH7110_CPU_CORE),
+ JH7110_GATE(JH7110_U7_DEBUG_CLK, "u0_u7mc_sft7110_debug_clk",
+ 0, JH7110_CPU_BUS),
+ JH7110__DIV(JH7110_U7_RTC_TOGGLE, "u0_u7mc_sft7110_rtc_toggle",
+ 6, JH7110_OSC),
+ JH7110_GATE(JH7110_U7_TRACE_CLK0, "u0_u7mc_sft7110_trace_clk0",
+ 0, JH7110_CPU_CORE),
+ JH7110_GATE(JH7110_U7_TRACE_CLK1, "u0_u7mc_sft7110_trace_clk1",
+ 0, JH7110_CPU_CORE),
+ JH7110_GATE(JH7110_U7_TRACE_CLK2, "u0_u7mc_sft7110_trace_clk2",
+ 0, JH7110_CPU_CORE),
+ JH7110_GATE(JH7110_U7_TRACE_CLK3, "u0_u7mc_sft7110_trace_clk3",
+ 0, JH7110_CPU_CORE),
+ JH7110_GATE(JH7110_U7_TRACE_CLK4, "u0_u7mc_sft7110_trace_clk4",
+ 0, JH7110_CPU_CORE),
+ JH7110_GATE(JH7110_U7_TRACE_COM_CLK, "u0_u7mc_sft7110_trace_com_clk",
+ 0, JH7110_CPU_BUS),
+ //NOC
+ JH7110_GATE(JH7110_NOC_BUS_CLK_CPU_AXI,
+ "u0_sft7110_noc_bus_clk_cpu_axi",
+ 0, JH7110_CPU_BUS),
+ JH7110_GATE(JH7110_NOC_BUS_CLK_AXICFG0_AXI,
+ "u0_sft7110_noc_bus_clk_axicfg0_axi",
+ 0, JH7110_AXI_CFG0),
+ //DDRC
+ JH7110__DIV(JH7110_OSC_DIV2, "osc_div2", 2, JH7110_OSC),
+ JH7110__DIV(JH7110_PLL1_DIV4, "pll1_div4", 2, JH7110_PLL1_DIV2),
+ JH7110__DIV(JH7110_PLL1_DIV8, "pll1_div8", 2, JH7110_PLL1_DIV4),
+ JH7110__MUX(JH7110_DDR_BUS, "ddr_bus", 4,
+ JH7110_OSC_DIV2,
+ JH7110_PLL1_DIV2,
+ JH7110_PLL1_DIV4,
+ JH7110_PLL1_DIV8),
+ JH7110_GATE(JH7110_DDR_CLK_AXI, "u0_ddr_sft7110_clk_axi",
+ 0, JH7110_DDR_BUS),
+ //GPU
+ JH7110__DIV(JH7110_GPU_CORE, "gpu_core", 7, JH7110_GPU_ROOT),
+ JH7110_GATE(JH7110_GPU_CORE_CLK, "u0_img_gpu_core_clk",
+ 0, JH7110_GPU_CORE),
+ JH7110_GATE(JH7110_GPU_SYS_CLK, "u0_img_gpu_sys_clk",
+ 0, JH7110_AXI_CFG1),
+ JH7110_GATE(JH7110_GPU_CLK_APB, "u0_img_gpu_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GDIV(JH7110_GPU_RTC_TOGGLE, "u0_img_gpu_rtc_toggle",
+ 0, 12, JH7110_OSC),
+ JH7110_GATE(JH7110_NOC_BUS_CLK_GPU_AXI,
+ "u0_sft7110_noc_bus_clk_gpu_axi",
+ 0, JH7110_GPU_CORE),
+ //ISP
+ JH7110_GATE(JH7110_ISP_TOP_CLK_ISPCORE_2X,
+ "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
+ 0, JH7110_ISP_2X),
+ JH7110_GATE(JH7110_ISP_TOP_CLK_ISP_AXI,
+ "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
+ 0, JH7110_ISP_AXI),
+ JH7110_GATE(JH7110_NOC_BUS_CLK_ISP_AXI,
+ "u0_sft7110_noc_bus_clk_isp_axi",
+ 0, JH7110_ISP_AXI),
+ //HIFI4
+ JH7110__DIV(JH7110_HIFI4_CORE, "hifi4_core", 15, JH7110_BUS_ROOT),
+ JH7110__DIV(JH7110_HIFI4_AXI, "hifi4_axi", 2, JH7110_HIFI4_CORE),
+ //AXICFG1_DEC
+ JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_MAIN, "u0_axi_cfg1_dec_clk_main",
+ 0, JH7110_AXI_CFG1),
+ JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_AHB, "u0_axi_cfg1_dec_clk_ahb",
+ 0, JH7110_AHB0),
+ //VOUT
+ JH7110_GATE(JH7110_VOUT_SRC,
+ "u0_dom_vout_top_clk_dom_vout_top_clk_vout_src",
+ 0, JH7110_VOUT_ROOT),
+ JH7110__DIV(JH7110_VOUT_AXI, "vout_axi", 7, JH7110_VOUT_ROOT),
+ JH7110_GATE(JH7110_NOC_BUS_CLK_DISP_AXI,
+ "u0_sft7110_noc_bus_clk_disp_axi",
+ 0, JH7110_VOUT_AXI),
+ JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AHB,
+ "u0_dom_vout_top_clk_dom_vout_top_clk_vout_ahb",
+ 0, JH7110_AHB1),
+ JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AXI,
+ "u0_dom_vout_top_clk_dom_vout_top_clk_vout_axi",
+ 0, JH7110_VOUT_AXI),
+ JH7110_GATE(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK,
+ "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_mclk",
+ 0, JH7110_MCLK),
+ JH7110__DIV(JH7110_VOUT_TOP_CLK_MIPIPHY_REF,
+ "u0_dom_vout_top_clk_dom_vout_top_clk_mipiphy_ref",
+ 2, JH7110_OSC),
+ //JPEGC
+ JH7110__DIV(JH7110_JPEGC_AXI, "jpegc_axi", 16, JH7110_VENC_ROOT),
+ JH7110_GATE(JH7110_CODAJ12_CLK_AXI, "u0_CODAJ12_clk_axi",
+ 0, JH7110_JPEGC_AXI),
+ JH7110_GDIV(JH7110_CODAJ12_CLK_CORE, "u0_CODAJ12_clk_core",
+ 0, 16, JH7110_VENC_ROOT),
+ JH7110_GATE(JH7110_CODAJ12_CLK_APB, "u0_CODAJ12_clk_apb",
+ 0, JH7110_APB12),
+ //VDEC
+ JH7110__DIV(JH7110_VDEC_AXI, "vdec_axi", 7, JH7110_BUS_ROOT),
+ JH7110_GATE(JH7110_WAVE511_CLK_AXI, "u0_WAVE511_clk_axi",
+ 0, JH7110_VDEC_AXI),
+ JH7110_GDIV(JH7110_WAVE511_CLK_BPU, "u0_WAVE511_clk_bpu",
+ 0, 7, JH7110_BUS_ROOT),
+ JH7110_GDIV(JH7110_WAVE511_CLK_VCE, "u0_WAVE511_clk_vce",
+ 0, 7, JH7110_VDEC_ROOT),
+ JH7110_GATE(JH7110_WAVE511_CLK_APB, "u0_WAVE511_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_VDEC_JPG_ARB_JPGCLK, "u0_vdec_jpg_arb_jpgclk",
+ 0, JH7110_JPEGC_AXI),
+ JH7110_GATE(JH7110_VDEC_JPG_ARB_MAINCLK, "u0_vdec_jpg_arb_mainclk",
+ 0, JH7110_VDEC_AXI),
+ JH7110_GATE(JH7110_NOC_BUS_CLK_VDEC_AXI,
+ "u0_sft7110_noc_bus_clk_vdec_axi",
+ 0, JH7110_VDEC_AXI),
+ //VENC
+ JH7110__DIV(JH7110_VENC_AXI, "venc_axi", 15, JH7110_VENC_ROOT),
+ JH7110_GATE(JH7110_WAVE420L_CLK_AXI, "u0_wave420l_clk_axi",
+ 0, JH7110_VENC_AXI),
+ JH7110_GDIV(JH7110_WAVE420L_CLK_BPU, "u0_wave420l_clk_bpu",
+ 0, 15, JH7110_VENC_ROOT),
+ JH7110_GDIV(JH7110_WAVE420L_CLK_VCE, "u0_wave420l_clk_vce",
+ 0, 15, JH7110_VENC_ROOT),
+ JH7110_GATE(JH7110_WAVE420L_CLK_APB, "u0_wave420l_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_NOC_BUS_CLK_VENC_AXI,
+ "u0_sft7110_noc_bus_clk_venc_axi",
+ 0, JH7110_VENC_AXI),
+ //INTMEM
+ JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV,
+ "u0_axi_cfg0_dec_clk_main_div",
+ 0, JH7110_AHB1),
+ JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_MAIN, "u0_axi_cfg0_dec_clk_main",
+ 0, JH7110_AXI_CFG0),
+ JH7110_GATE(JH7110_AXI_CFG0_DEC_CLK_HIFI4, "u0_axi_cfg0_dec_clk_hifi4",
+ 0, JH7110_HIFI4_AXI),
+ JH7110_GATE(JH7110_AXIMEM2_128B_CLK_AXI, "u2_aximem_128b_clk_axi",
+ 0, JH7110_AXI_CFG0),
+ //QSPI
+ JH7110_GATE(JH7110_QSPI_CLK_AHB, "u0_cdns_qspi_clk_ahb",
+ 0, JH7110_AHB1),
+ JH7110_GATE(JH7110_QSPI_CLK_APB, "u0_cdns_qspi_clk_apb",
+ 0, JH7110_APB12),
+ JH7110__DIV(JH7110_QSPI_REF_SRC, "u0_cdns_qspi_ref_src",
+ 16, JH7110_GMACUSB_ROOT),
+ JH7110_GMUX(JH7110_QSPI_CLK_REF, "u0_cdns_qspi_clk_ref", 0, 2,
+ JH7110_OSC,
+ JH7110_QSPI_REF_SRC),
+ //SDIO
+ JH7110_GATE(JH7110_SDIO0_CLK_AHB, "u0_dw_sdio_clk_ahb",
+ 0, JH7110_AHB0),
+ JH7110_GATE(JH7110_SDIO1_CLK_AHB, "u1_dw_sdio_clk_ahb",
+ 0, JH7110_AHB0),
+ JH7110_GDIV(JH7110_SDIO0_CLK_SDCARD, "u0_dw_sdio_clk_sdcard",
+ 0, 15, JH7110_AXI_CFG0),
+ JH7110_GDIV(JH7110_SDIO1_CLK_SDCARD, "u1_dw_sdio_clk_sdcard",
+ 0, 15, JH7110_AXI_CFG0),
+ //STG
+ JH7110__DIV(JH7110_USB_125M, "usb_125m", 15, JH7110_GMACUSB_ROOT),
+ JH7110_GATE(JH7110_NOC_BUS_CLK_STG_AXI,
+ "u0_sft7110_noc_bus_clk_stg_axi",
+ 0, JH7110_NOCSTG_BUS),
+ //GMAC1
+ JH7110_GATE(JH7110_GMAC5_CLK_AHB, "u1_dw_gmac5_axi64_clk_ahb",
+ 0, JH7110_AHB0),
+ JH7110_GATE(JH7110_GMAC5_CLK_AXI, "u1_dw_gmac5_axi64_clk_axi",
+ 0, JH7110_STG_AXIAHB),
+ JH7110__DIV(JH7110_GMAC_SRC, "gmac_src", 7, JH7110_GMACUSB_ROOT),
+ JH7110__DIV(JH7110_GMAC1_GTXCLK, "gmac1_gtxclk",
+ 15, JH7110_GMACUSB_ROOT),
+ JH7110__DIV(JH7110_GMAC1_RMII_RTX, "gmac1_rmii_rtx",
+ 30, JH7110_GMAC1_RMII_REFIN),
+ JH7110_GDIV(JH7110_GMAC5_CLK_PTP, "u1_dw_gmac5_axi64_clk_ptp",
+ 0, 31, JH7110_GMAC_SRC),
+ JH7110__MUX(JH7110_GMAC5_CLK_RX, "u1_dw_gmac5_axi64_clk_rx", 2,
+ JH7110_GMAC1_RGMII_RXIN,
+ JH7110_GMAC1_RMII_RTX),
+ JH7110__INV(JH7110_GMAC5_CLK_RX_INV, "u1_dw_gmac5_axi64_clk_rx_inv",
+ JH7110_GMAC5_CLK_RX),
+ JH7110_GMUX(JH7110_GMAC5_CLK_TX, "u1_dw_gmac5_axi64_clk_tx", 0, 2,
+ JH7110_GMAC1_GTXCLK,
+ JH7110_GMAC1_RMII_RTX),
+ JH7110__INV(JH7110_GMAC5_CLK_TX_INV, "u1_dw_gmac5_axi64_clk_tx_inv",
+ JH7110_GMAC5_CLK_TX),
+ JH7110_GATE(JH7110_GMAC1_GTXC, "gmac1_gtxc",
+ 0, JH7110_GMAC1_GTXCLK),
+ //GMAC0
+ JH7110_GDIV(JH7110_GMAC0_GTXCLK, "gmac0_gtxclk",
+ 0, 15, JH7110_GMACUSB_ROOT),
+ JH7110_GDIV(JH7110_GMAC0_PTP, "gmac0_ptp",
+ 0, 31, JH7110_GMAC_SRC),
+ JH7110_GDIV(JH7110_GMAC_PHY, "gmac_phy",
+ 0, 31, JH7110_GMAC_SRC),
+ JH7110_GATE(JH7110_GMAC0_GTXC, "gmac0_gtxc",
+ 0, JH7110_GMAC0_GTXCLK),
+ //SYS MISC
+ JH7110_GATE(JH7110_SYS_IOMUX_PCLK, "u0_sys_iomux_pclk",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_MAILBOX_CLK_APB, "u0_mailbox_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_INT_CTRL_CLK_APB, "u0_int_ctrl_clk_apb",
+ 0, JH7110_APB12),
+ //CAN
+ JH7110_GATE(JH7110_CAN0_CTRL_CLK_APB, "u0_can_ctrl_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GDIV(JH7110_CAN0_CTRL_CLK_TIMER, "u0_can_ctrl_clk_timer",
+ 0, 24, JH7110_OSC),
+ JH7110_GDIV(JH7110_CAN0_CTRL_CLK_CAN, "u0_can_ctrl_clk_can",
+ 0, 63, JH7110_PERH_ROOT),
+ JH7110_GATE(JH7110_CAN1_CTRL_CLK_APB, "u1_can_ctrl_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GDIV(JH7110_CAN1_CTRL_CLK_TIMER, "u1_can_ctrl_clk_timer",
+ 0, 24, JH7110_OSC),
+ JH7110_GDIV(JH7110_CAN1_CTRL_CLK_CAN, "u1_can_ctrl_clk_can",
+ 0, 63, JH7110_PERH_ROOT),
+ //PWM
+ JH7110_GATE(JH7110_PWM_CLK_APB, "u0_pwm_8ch_clk_apb",
+ 0, JH7110_APB12),
+ //WDT
+ JH7110_GATE(JH7110_DSKIT_WDT_CLK_APB, "u0_dskit_wdt_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_DSKIT_WDT_CLK_WDT, "u0_dskit_wdt_clk_wdt",
+ 0, JH7110_OSC),
+ //TIMER
+ JH7110_GATE(JH7110_TIMER_CLK_APB, "u0_si5_timer_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_TIMER_CLK_TIMER0, "u0_si5_timer_clk_timer0",
+ 0, JH7110_OSC),
+ JH7110_GATE(JH7110_TIMER_CLK_TIMER1, "u0_si5_timer_clk_timer1",
+ 0, JH7110_OSC),
+ JH7110_GATE(JH7110_TIMER_CLK_TIMER2, "u0_si5_timer_clk_timer2",
+ 0, JH7110_OSC),
+ JH7110_GATE(JH7110_TIMER_CLK_TIMER3, "u0_si5_timer_clk_timer3",
+ 0, JH7110_OSC),
+ //TEMP SENSOR
+ JH7110_GATE(JH7110_TEMP_SENSOR_CLK_APB, "u0_temp_sensor_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GDIV(JH7110_TEMP_SENSOR_CLK_TEMP, "u0_temp_sensor_clk_temp",
+ 0, 24, JH7110_OSC),
+ //SPI
+ JH7110_GATE(JH7110_SPI0_CLK_APB, "u0_ssp_spi_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GATE(JH7110_SPI1_CLK_APB, "u1_ssp_spi_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GATE(JH7110_SPI2_CLK_APB, "u2_ssp_spi_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GATE(JH7110_SPI3_CLK_APB, "u3_ssp_spi_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_SPI4_CLK_APB, "u4_ssp_spi_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_SPI5_CLK_APB, "u5_ssp_spi_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_SPI6_CLK_APB, "u6_ssp_spi_clk_apb",
+ 0, JH7110_APB12),
+ //I2C
+ JH7110_GATE(JH7110_I2C0_CLK_APB, "u0_dw_i2c_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GATE(JH7110_I2C1_CLK_APB, "u1_dw_i2c_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GATE(JH7110_I2C2_CLK_APB, "u2_dw_i2c_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GATE(JH7110_I2C3_CLK_APB, "u3_dw_i2c_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_I2C4_CLK_APB, "u4_dw_i2c_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_I2C5_CLK_APB, "u5_dw_i2c_clk_apb",
+ 0, JH7110_APB12),
+ JH7110_GATE(JH7110_I2C6_CLK_APB, "u6_dw_i2c_clk_apb",
+ 0, JH7110_APB12),
+ //UART
+ JH7110_GATE(JH7110_UART0_CLK_APB, "u0_dw_uart_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GATE(JH7110_UART0_CLK_CORE, "u0_dw_uart_clk_core",
+ 0, JH7110_OSC),
+ JH7110_GATE(JH7110_UART1_CLK_APB, "u1_dw_uart_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GATE(JH7110_UART1_CLK_CORE, "u1_dw_uart_clk_core",
+ 0, JH7110_OSC),
+ JH7110_GATE(JH7110_UART2_CLK_APB, "u2_dw_uart_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GATE(JH7110_UART2_CLK_CORE, "u2_dw_uart_clk_core",
+ 0, JH7110_OSC),
+ JH7110_GATE(JH7110_UART3_CLK_APB, "u3_dw_uart_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GDIV(JH7110_UART3_CLK_CORE, "u3_dw_uart_clk_core",
+ 0, 131071, JH7110_PERH_ROOT),
+ JH7110_GATE(JH7110_UART4_CLK_APB, "u4_dw_uart_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GDIV(JH7110_UART4_CLK_CORE, "u4_dw_uart_clk_core",
+ 0, 131071, JH7110_PERH_ROOT),
+ JH7110_GATE(JH7110_UART5_CLK_APB, "u5_dw_uart_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GDIV(JH7110_UART5_CLK_CORE, "u5_dw_uart_clk_core",
+ 0, 131071, JH7110_PERH_ROOT),
+ //PWMDAC
+ JH7110_GATE(JH7110_PWMDAC_CLK_APB, "u0_pwmdac_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GDIV(JH7110_PWMDAC_CLK_CORE, "u0_pwmdac_clk_core",
+ 0, 256, JH7110_AUDIO_ROOT),
+ //SPDIF
+ JH7110_GATE(JH7110_SPDIF_CLK_APB, "u0_cdns_spdif_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GATE(JH7110_SPDIF_CLK_CORE, "u0_cdns_spdif_clk_core",
+ 0, JH7110_MCLK),
+ //I2STX0_4CH0
+ JH7110_GATE(JH7110_I2STX0_4CHCLK_APB, "u0_i2stx_4ch_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GDIV(JH7110_I2STX_4CH0_BCLK_MST, "i2stx_4ch0_bclk_mst",
+ 0, 32, JH7110_MCLK),
+ JH7110__INV(JH7110_I2STX_4CH0_BCLK_MST_INV, "i2stx_4ch0_bclk_mst_inv",
+ JH7110_I2STX_4CH0_BCLK_MST),
+ JH7110_MDIV(JH7110_I2STX_4CH0_LRCK_MST, "i2stx_4ch0_lrck_mst", 64, 2,
+ JH7110_I2STX_4CH0_BCLK_MST_INV,
+ JH7110_I2STX_4CH0_BCLK_MST),
+ JH7110__MUX(JH7110_I2STX0_4CHBCLK, "u0_i2stx_4ch_bclk", 2,
+ JH7110_I2STX_4CH0_BCLK_MST,
+ JH7110_I2STX_BCLK_EXT),
+ JH7110__INV(JH7110_I2STX0_4CHBCLK_N, "u0_i2stx_4ch_bclk_n",
+ JH7110_I2STX0_4CHBCLK),
+ JH7110__MUX(JH7110_I2STX0_4CHLRCK, "u0_i2stx_4ch_lrck", 2,
+ JH7110_I2STX_4CH0_LRCK_MST,
+ JH7110_I2STX_LRCK_EXT),
+ //I2STX1_4CH0
+ JH7110_GATE(JH7110_I2STX1_4CHCLK_APB, "u1_i2stx_4ch_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GDIV(JH7110_I2STX_4CH1_BCLK_MST, "i2stx_4ch1_bclk_mst",
+ 0, 32, JH7110_MCLK),
+ JH7110__INV(JH7110_I2STX_4CH1_BCLK_MST_INV, "i2stx_4ch1_bclk_mst_inv",
+ JH7110_I2STX_4CH1_BCLK_MST),
+ JH7110_MDIV(JH7110_I2STX_4CH1_LRCK_MST, "i2stx_4ch1_lrck_mst", 64, 2,
+ JH7110_I2STX_4CH1_BCLK_MST_INV,
+ JH7110_I2STX_4CH1_BCLK_MST),
+ JH7110__MUX(JH7110_I2STX1_4CHBCLK, "u1_i2stx_4ch_bclk", 2,
+ JH7110_I2STX_4CH1_BCLK_MST,
+ JH7110_I2STX_BCLK_EXT),
+ JH7110__INV(JH7110_I2STX1_4CHBCLK_N, "u1_i2stx_4ch_bclk_n",
+ JH7110_I2STX1_4CHBCLK),
+ JH7110__MUX(JH7110_I2STX1_4CHLRCK, "u1_i2stx_4ch_lrck", 2,
+ JH7110_I2STX_4CH1_LRCK_MST,
+ JH7110_I2STX_LRCK_EXT),
+ //I2SRX_3CH
+ JH7110_GATE(JH7110_I2SRX0_3CH_CLK_APB, "u0_i2srx_3ch_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GDIV(JH7110_I2SRX_3CH_BCLK_MST, "i2srx_3ch_bclk_mst",
+ 0, 32, JH7110_MCLK),
+ JH7110__INV(JH7110_I2SRX_3CH_BCLK_MST_INV, "i2srx_3ch_bclk_mst_inv",
+ JH7110_I2SRX_3CH_BCLK_MST),
+ JH7110_MDIV(JH7110_I2SRX_3CH_LRCK_MST, "i2srx_3ch_lrck_mst", 64, 2,
+ JH7110_I2SRX_3CH_BCLK_MST_INV,
+ JH7110_I2SRX_3CH_BCLK_MST),
+ JH7110__MUX(JH7110_I2SRX0_3CH_BCLK, "u0_i2srx_3ch_bclk", 2,
+ JH7110_I2SRX_3CH_BCLK_MST,
+ JH7110_I2SRX_BCLK_EXT),
+ JH7110__INV(JH7110_I2SRX0_3CH_BCLK_N, "u0_i2srx_3ch_bclk_n",
+ JH7110_I2SRX0_3CH_BCLK),
+ JH7110__MUX(JH7110_I2SRX0_3CH_LRCK, "u0_i2srx_3ch_lrck", 2,
+ JH7110_I2SRX_3CH_LRCK_MST,
+ JH7110_I2SRX_LRCK_EXT),
+ //PDM_4MIC
+ JH7110_GDIV(JH7110_PDM_CLK_DMIC, "u0_pdm_4mic_clk_dmic",
+ 0, 64, JH7110_MCLK),
+ JH7110_GATE(JH7110_PDM_CLK_APB, "u0_pdm_4mic_clk_apb",
+ 0, JH7110_APB0),
+ //TDM
+ JH7110_GATE(JH7110_TDM_CLK_AHB, "u0_tdm16slot_clk_ahb",
+ 0, JH7110_AHB0),
+ JH7110_GATE(JH7110_TDM_CLK_APB, "u0_tdm16slot_clk_apb",
+ 0, JH7110_APB0),
+ JH7110_GDIV(JH7110_TDM_INTERNAL, "tdm_internal",
+ 0, 64, JH7110_MCLK),
+ JH7110__MUX(JH7110_TDM_CLK_TDM, "u0_tdm16slot_clk_tdm", 2,
+ JH7110_TDM_INTERNAL,
+ JH7110_TDM_EXT),
+ JH7110__INV(JH7110_TDM_CLK_TDM_N, "u0_tdm16slot_clk_tdm_n",
+ JH7110_TDM_CLK_TDM),
+ JH7110__DIV(JH7110_JTAG_CERTIFICATION_TRNG_CLK,
+ "u0_jtag_certification_trng_clk", 4, JH7110_OSC),
+};
+
+const int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev,
+ struct jh7110_clk_priv *priv)
+{
+ unsigned int idx;
+ int ret = 0;
+
+ priv->sys_base = devm_platform_ioremap_resource_byname(pdev, "sys");
+ if (IS_ERR(priv->sys_base))
+ return PTR_ERR(priv->sys_base);
+
+ priv->pll[PLL_OF(JH7110_PLL0_OUT)] =
+ clk_hw_register_fixed_rate(priv->dev,
+ "pll0_out", "osc", 0, 1250000000);
+ if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL0_OUT)]))
+ return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL0_OUT)]);
+
+ priv->pll[PLL_OF(JH7110_PLL1_OUT)] =
+ clk_hw_register_fixed_rate(priv->dev,
+ "pll1_out", "osc", 0, 1066000000);
+ if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]))
+ return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL1_OUT)]);
+
+ priv->pll[PLL_OF(JH7110_PLL2_OUT)] =
+ clk_hw_register_fixed_rate(priv->dev,
+ "pll2_out", "osc", 0, 1228800000);
+ if (IS_ERR(priv->pll[PLL_OF(JH7110_PLL2_OUT)]))
+ return PTR_ERR(priv->pll[PLL_OF(JH7110_PLL2_OUT)]);
+
+ priv->pll[PLL_OF(JH7110_AON_APB)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "aon_apb", "apb_bus_func", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_RESET1_CTRL_CLK_SRC)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_reset_ctrl_clk_src", "osc", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_DDR_ROOT)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "ddr_root", "pll1_out", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_VDEC_ROOT)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "vdec_root", "pll0_out", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_VENC_ROOT)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "venc_root", "pll2_out", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_VOUT_ROOT)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "vout_root", "pll2_out", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_GMACUSB_ROOT)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "gmacusb_root", "pll0_out", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PCLK2_MUX_FUNC_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u2_pclk_mux_func_pclk", "apb_bus_func", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PCLK2_MUX_BIST_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u2_pclk_mux_bist_pclk", "bist_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_APB_BUS)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "apb_bus", "u2_pclk_mux_pclk", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_APB12)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "apb12", "apb_bus", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_AXI_CFG1)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "axi_cfg1", "isp_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK0)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_pll_wrap_crg_gclk0", "gclk0", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK1)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_pll_wrap_crg_gclk1", "gclk1", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PLL_WRAP_CRG_GCLK2)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_pll_wrap_crg_gclk2", "gclk2", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_JTAG2APB_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_jtag2apb_pclk", "bist_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_U7_BUS_CLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_u7mc_sft7110_bus_clk", "cpu_bus", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_U7_IRQ_SYNC_BUS_CLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_u7mc_sft7110_irq_sync_bus_clk", "cpu_bus", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_CPU_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk2_cpu_axi",
+ "u0_sft7110_noc_bus_clk_cpu_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK_APB_BUS)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk_apb_bus", "apb_bus", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_APB_BUS)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk2_apb_bus",
+ "u0_sft7110_noc_bus_clk_apb_bus", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_AXICFG0_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk2_axicfg0_axi",
+ "u0_sft7110_noc_bus_clk_axicfg0_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_DDR_CLK_DDRPHY_PLL_BYPASS)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_ddr_sft7110_clk_ddrphy_pll_bypass",
+ "pll1_out", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_DDR_CLK_OSC)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_ddr_sft7110_clk_osc", "osc", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_DDR_CLK_APB)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_ddr_sft7110_clk_apb", "apb12", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK_DDRC)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk_ddrc", "ddr_bus", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_DDRC)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk2_ddrc",
+ "u0_sft7110_noc_bus_clk_ddrc", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SYS_AHB_DEC_CLK_AHB)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_saif_amba_sys_ahb_dec_clk_ahb", "ahb0", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_STG_AHB_DEC_CLK_AHB)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_saif_amba_stg_ahb_dec_clk_ahb", "ahb0", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_GPU_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk2_gpu_axi",
+ "u0_sft7110_noc_bus_clk_gpu_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_ISP_TOP_CLK_DVP)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
+ "dvp_clk", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_ISP_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk2_isp_axi",
+ "u0_sft7110_noc_bus_clk_isp_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_ISP_TOP_CLK_BIST_APB)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_dom_isp_top_clk_dom_isp_top_clk_bist_apb",
+ "bist_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_DISP_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk2_disp_axi",
+ "u0_sft7110_noc_bus_clk_disp_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_VOUT_TOP_CLK_HDMITX0_BCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_dom_vout_top_clk_dom_vout_top_clk_hdmitx0_bclk",
+ "u0_i2stx_4ch_bclk", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_VOUT_TOP_U0_HDMI_TX_PIN_WS)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_dom_vout_top_u0_hdmi_tx_pin_ws",
+ "u0_i2stx_4ch_lrck", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_VOUT_TOP_CLK_HDMIPHY_REF)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_dom_vout_top_clk_dom_vout_top_clk_hdmiphy_ref",
+ "osc", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_VOUT_TOP_BIST_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_dom_vout_top_clk_dom_vout_top_bist_pclk",
+ "bist_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_AXIMEM0_128B_CLK_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_aximem_128b_clk_axi",
+ "u0_WAVE511_clk_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_VDEC_INTSRAM_CLK_VDEC_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_vdec_intsram_clk_vdec_axi",
+ "u0_aximem_128b_clk_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_VDEC_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk2_vdec_axi",
+ "u0_sft7110_noc_bus_clk_vdec_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_AXIMEM1_128B_CLK_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_aximem_128b_clk_axi",
+ "u0_wave420l_clk_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_VENC_INTSRAM_CLK_VENC_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_venc_intsram_clk_venc_axi",
+ "u0_wave420l_clk_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_VENC_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk2_venc_axi",
+ "u0_sft7110_noc_bus_clk_venc_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SRAM_CLK_ROM)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_intmem_rom_sram_clk_rom",
+ "u2_aximem_128b_clk_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_NOC_BUS_CLK2_STG_AXI)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sft7110_noc_bus_clk2_stg_axi",
+ "u0_sft7110_noc_bus_clk_stg_axi", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_GMAC5_CLK_RMII)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_dw_gmac5_axi64_clk_rmii",
+ "gmac1_rmii_refin", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_AON_AHB)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "aon_ahb", "stg_axiahb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SYS_CRG_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sys_crg_pclk", "apb12", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SYS_SYSCON_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sys_syscon_pclk", "apb12", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SPI0_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_ssp_spi_clk_core", "u0_ssp_spi_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SPI1_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_ssp_spi_clk_core", "u1_ssp_spi_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SPI2_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u2_ssp_spi_clk_core", "u2_ssp_spi_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SPI3_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u3_ssp_spi_clk_core", "u3_ssp_spi_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SPI4_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u4_ssp_spi_clk_core", "u4_ssp_spi_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SPI5_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u5_ssp_spi_clk_core", "u5_ssp_spi_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SPI6_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u6_ssp_spi_clk_core", "u6_ssp_spi_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2C0_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_dw_i2c_clk_core", "u0_dw_i2c_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2C1_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_dw_i2c_clk_core", "u1_dw_i2c_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2C2_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2C3_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u3_dw_i2c_clk_core", "u3_dw_i2c_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2C4_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u4_dw_i2c_clk_core", "u4_dw_i2c_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2C5_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2C6_CLK_CORE)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u6_dw_i2c_clk_core", "u6_dw_i2c_clk_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2STX_BCLK_MST)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "i2stx_bclk_mst", "i2stx_4ch1_bclk_mst", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2STX_LRCK_MST)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "i2stx_lrck_mst", "i2stx_4ch1_lrck_mst", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2SRX_BCLK_MST)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "i2srx_bclk_mst", "i2srx_3ch_bclk_mst", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_I2SRX_LRCK_MST)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "i2srx_lrck_mst", "i2srx_3ch_lrck_mst", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC0_BCLK_SLV)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_pdm_4mic_clk_dmic0_bclk_slv",
+ "u0_i2srx_3ch_bclk", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC0_LRCK_SLV)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_pdm_4mic_clk_dmic0_lrck_slv",
+ "u0_i2srx_3ch_lrck", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC1_BCLK_SLV)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_pdm_4mic_clk_dmic1_bclk_slv",
+ "u0_i2srx_3ch_bclk", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_PDM_CLK_DMIC1_LRCK_SLV)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_pdm_4mic_clk_dmic1_lrck_slv",
+ "u0_i2srx_3ch_lrck", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_TDM_CLK_MST)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "tdm_clk_mst", "ahb0", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_AHB2APB_CLK_AHB)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_ahb2apb_clk_ahb", "tdm_internal", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_P2P_ASYNC_CLK_APBS)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_p2p_async_clk_apbs", "apb0", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_P2P_ASYNC_CLK_APBM)] = \
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u1_p2p_async_clk_apbm", "aon_apb", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_JTAG_DAISY_CHAIN_JTAG_TCK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_jtag_daisy_chain_JTAG_TCK",
+ "jtag_tck_inner", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_U7_DEBUG_SYSTEMJTAG_JTAG_TCK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_u7mc_sft7110_debug_systemjtag_jtag_TCK",
+ "u0_jtag_daisy_chain_jtag_tck_0", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_E2_DEBUG_SYSTEMJTAG_TCK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_e2_sft7110_debug_systemjtag_jtag_TCK",
+ "u0_jtag_daisy_chain_jtag_tck_1", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_JTAG_CERTIFICATION_TCK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_jtag_certification_tck",
+ "jtag_tck_inner", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_SEC_SKP_CLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u0_sec_top_skp_clk",
+ "u0_jtag_certification_trng_clk", 0, 1, 1);
+ priv->pll[PLL_OF(JH7110_U2_PCLK_MUX_PCLK)] =
+ devm_clk_hw_register_fixed_factor(priv->dev,
+ "u2_pclk_mux_pclk",
+ "u2_pclk_mux_func_pclk", 0, 1, 1);
+
+
+ for (idx = 0; idx < JH7110_CLK_SYS_REG_END; idx++) {
+ u32 max = jh7110_clk_sys_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_clk_sys_data[idx].name,
+ .ops = starfive_jh7110_clk_ops(max),
+ .parent_data = parents,
+ .num_parents = ((max & JH7110_CLK_MUX_MASK) \
+ >> JH7110_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_clk_sys_data[idx].flags,
+ };
+ struct jh7110_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_clk_sys_data[idx].parents[i];
+
+ if (pidx < JH7110_CLK_SYS_REG_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if ((pidx < JH7110_CLK_SYS_END) && \
+ (pidx > JH7110_CLK_SYS_REG_END))
+ parents[i].hw = priv->pll[PLL_OF(pidx)];
+ else if (pidx == JH7110_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JH7110_GMAC1_RMII_REFIN)
+ parents[i].fw_name = "gmac1_rmii_refin";
+ else if (pidx == JH7110_GMAC1_RGMII_RXIN)
+ parents[i].fw_name = "gmac1_rgmii_rxin";
+ else if (pidx == JH7110_I2STX_BCLK_EXT)
+ parents[i].fw_name = "i2stx_bclk_ext";
+ else if (pidx == JH7110_I2STX_LRCK_EXT)
+ parents[i].fw_name = "i2stx_lrck_ext";
+ else if (pidx == JH7110_I2SRX_BCLK_EXT)
+ parents[i].fw_name = "i2srx_bclk_ext";
+ else if (pidx == JH7110_I2SRX_LRCK_EXT)
+ parents[i].fw_name = "i2srx_lrck_ext";
+ else if (pidx == JH7110_TDM_EXT)
+ parents[i].fw_name = "tdm_ext";
+ else if (pidx == JH7110_MCLK_EXT)
+ parents[i].fw_name = "mclk_ext";
+ else if (pidx == JH7110_JTAG_TCK_INNER)
+ parents[i].fw_name = "jtag_tclk_inner";
+ else if (pidx == JH7110_BIST_APB)
+ parents[i].fw_name = "bist_apb";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH7110_CLK_DIV_MASK;
+ clk->reg_flags = JH7110_CLK_SYS_FLAG;
+
+ ret = devm_clk_hw_register(priv->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ dev_dbg(&pdev->dev,"starfive JH7110 clk_sys init successfully.");
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Clock Generator Driver
+ *
+ * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com>
+ */
+
+#ifndef _CLK_STARFIVE_JH7110_H_
+#define _CLK_STARFIVE_JH7110_H_
+
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+
+/* register flags */
+#define JH7110_CLK_SYS_FLAG 1
+#define JH7110_CLK_STG_FLAG 2
+#define JH7110_CLK_AON_FLAG 3
+#define JH7110_CLK_VOUT_FLAG 4
+#define JH7110_CLK_ISP_FLAG 5
+
+/* register fields */
+#define JH7110_CLK_ENABLE BIT(31)
+#define JH7110_CLK_INVERT BIT(30)
+#define JH7110_CLK_MUX_MASK GENMASK(29, 24)
+#define JH7110_CLK_MUX_SHIFT 24
+#define JH7110_CLK_DIV_MASK GENMASK(23, 0)
+
+/* clkgen PLL CLOCK offset */
+#define PLL_OF(x) (x - JH7110_CLK_REG_END)
+
+/* clock data */
+struct jh7110_clk_data {
+ const char *name;
+ unsigned long flags;
+ u32 max;
+ u16 parents[4];
+};
+
+struct jh7110_clk {
+ struct clk_hw hw;
+ unsigned int idx;
+ unsigned int max_div;
+ unsigned int reg_flags;
+};
+
+struct jh7110_clk_priv {
+ /* protect clk enable and set rate/parent from happening at the same time */
+ spinlock_t rmw_lock;
+ struct device *dev;
+ void __iomem *sys_base;
+ void __iomem *stg_base;
+ void __iomem *aon_base;
+ void __iomem *vout_base;
+ void __iomem *isp_base;
+ struct clk_hw *pll[PLL_OF(JH7110_CLK_END)];
+ struct jh7110_clk reg[];
+};
+
+#define JH7110_GATE(_idx, _name, _flags, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = CLK_SET_RATE_PARENT | (_flags), \
+ .max = JH7110_CLK_ENABLE, \
+ .parents = { [0] = _parent }, \
+}
+
+#define JH7110__DIV(_idx, _name, _max, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = _max, \
+ .parents = { [0] = _parent }, \
+}
+
+#define JH7110_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = JH7110_CLK_ENABLE | (_max), \
+ .parents = { [0] = _parent }, \
+}
+
+#define JH7110__MUX(_idx, _name, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = ((_nparents) - 1) << JH7110_CLK_MUX_SHIFT, \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define JH7110_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = JH7110_CLK_ENABLE | \
+ (((_nparents) - 1) << JH7110_CLK_MUX_SHIFT), \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define JH7110_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = 0, \
+ .max = (((_nparents) - 1) << JH7110_CLK_MUX_SHIFT) | (_max), \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define JH7110__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = JH7110_CLK_ENABLE | \
+ (((_nparents) - 1) << JH7110_CLK_MUX_SHIFT) | (_max), \
+ .parents = { __VA_ARGS__ }, \
+}
+
+#define JH7110__INV(_idx, _name, _parent) [_idx] = { \
+ .name = _name, \
+ .flags = CLK_SET_RATE_PARENT, \
+ .max = JH7110_CLK_INVERT, \
+ .parents = { [0] = _parent }, \
+}
+
+void __iomem *jh7110_clk_reg_addr_get(struct jh7110_clk *clk);
+const struct clk_ops *starfive_jh7110_clk_ops(u32 max);
+
+const int __init clk_starfive_jh7110_sys_init(struct platform_device *pdev, \
+ struct jh7110_clk_priv *priv);
+const int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev, \
+ struct jh7110_clk_priv *priv);
+const int __init clk_starfive_jh7110_aon_init(struct platform_device *pdev, \
+ struct jh7110_clk_priv *priv);
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright 2022 StarFive, Inc <xingyu.wu@starfivetech.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLKGEN_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLKGEN_H__
+
+/* sys regisger */
+#define JH7110_CPU_ROOT 0
+#define JH7110_CPU_CORE 1
+#define JH7110_CPU_BUS 2
+#define JH7110_GPU_ROOT 3
+#define JH7110_PERH_ROOT 4
+#define JH7110_BUS_ROOT 5
+#define JH7110_NOCSTG_BUS 6
+#define JH7110_AXI_CFG0 7
+#define JH7110_STG_AXIAHB 8
+#define JH7110_AHB0 9
+#define JH7110_AHB1 10
+#define JH7110_APB_BUS_FUNC 11
+#define JH7110_APB0 12
+#define JH7110_PLL0_DIV2 13
+#define JH7110_PLL1_DIV2 14
+#define JH7110_PLL2_DIV2 15
+#define JH7110_AUDIO_ROOT 16
+#define JH7110_MCLK_INNER 17
+#define JH7110_MCLK 18
+#define JH7110_MCLK_OUT 19
+#define JH7110_ISP_2X 20
+#define JH7110_ISP_AXI 21
+#define JH7110_GCLK0 22
+#define JH7110_GCLK1 23
+#define JH7110_GCLK2 24
+#define JH7110_U7_CORE_CLK 25
+#define JH7110_U7_CORE_CLK1 26
+#define JH7110_U7_CORE_CLK2 27
+#define JH7110_U7_CORE_CLK3 28
+#define JH7110_U7_CORE_CLK4 29
+#define JH7110_U7_DEBUG_CLK 30
+#define JH7110_U7_RTC_TOGGLE 31
+#define JH7110_U7_TRACE_CLK0 32
+#define JH7110_U7_TRACE_CLK1 33
+#define JH7110_U7_TRACE_CLK2 34
+#define JH7110_U7_TRACE_CLK3 35
+#define JH7110_U7_TRACE_CLK4 36
+#define JH7110_U7_TRACE_COM_CLK 37
+#define JH7110_NOC_BUS_CLK_CPU_AXI 38
+#define JH7110_NOC_BUS_CLK_AXICFG0_AXI 39
+#define JH7110_OSC_DIV2 40
+#define JH7110_PLL1_DIV4 41
+#define JH7110_PLL1_DIV8 42
+#define JH7110_DDR_BUS 43
+#define JH7110_DDR_CLK_AXI 44
+#define JH7110_GPU_CORE 45
+#define JH7110_GPU_CORE_CLK 46
+#define JH7110_GPU_SYS_CLK 47
+#define JH7110_GPU_CLK_APB 48
+#define JH7110_GPU_RTC_TOGGLE 49
+#define JH7110_NOC_BUS_CLK_GPU_AXI 50
+#define JH7110_ISP_TOP_CLK_ISPCORE_2X 51
+#define JH7110_ISP_TOP_CLK_ISP_AXI 52
+#define JH7110_NOC_BUS_CLK_ISP_AXI 53
+#define JH7110_HIFI4_CORE 54
+#define JH7110_HIFI4_AXI 55
+#define JH7110_AXI_CFG1_DEC_CLK_MAIN 56
+#define JH7110_AXI_CFG1_DEC_CLK_AHB 57
+#define JH7110_VOUT_SRC 58
+#define JH7110_VOUT_AXI 59
+#define JH7110_NOC_BUS_CLK_DISP_AXI 60
+#define JH7110_VOUT_TOP_CLK_VOUT_AHB 61
+#define JH7110_VOUT_TOP_CLK_VOUT_AXI 62
+#define JH7110_VOUT_TOP_CLK_HDMITX0_MCLK 63
+#define JH7110_VOUT_TOP_CLK_MIPIPHY_REF 64
+#define JH7110_JPEGC_AXI 65
+#define JH7110_CODAJ12_CLK_AXI 66
+#define JH7110_CODAJ12_CLK_CORE 67
+#define JH7110_CODAJ12_CLK_APB 68
+#define JH7110_VDEC_AXI 69
+#define JH7110_WAVE511_CLK_AXI 70
+#define JH7110_WAVE511_CLK_BPU 71
+#define JH7110_WAVE511_CLK_VCE 72
+#define JH7110_WAVE511_CLK_APB 73
+#define JH7110_VDEC_JPG_ARB_JPGCLK 74
+#define JH7110_VDEC_JPG_ARB_MAINCLK 75
+#define JH7110_NOC_BUS_CLK_VDEC_AXI 76
+#define JH7110_VENC_AXI 77
+#define JH7110_WAVE420L_CLK_AXI 78
+#define JH7110_WAVE420L_CLK_BPU 79
+#define JH7110_WAVE420L_CLK_VCE 80
+#define JH7110_WAVE420L_CLK_APB 81
+#define JH7110_NOC_BUS_CLK_VENC_AXI 82
+#define JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV 83
+#define JH7110_AXI_CFG0_DEC_CLK_MAIN 84
+#define JH7110_AXI_CFG0_DEC_CLK_HIFI4 85
+#define JH7110_AXIMEM2_128B_CLK_AXI 86
+#define JH7110_QSPI_CLK_AHB 87
+#define JH7110_QSPI_CLK_APB 88
+#define JH7110_QSPI_REF_SRC 89
+#define JH7110_QSPI_CLK_REF 90
+#define JH7110_SDIO0_CLK_AHB 91
+#define JH7110_SDIO1_CLK_AHB 92
+#define JH7110_SDIO0_CLK_SDCARD 93
+#define JH7110_SDIO1_CLK_SDCARD 94
+#define JH7110_USB_125M 95
+#define JH7110_NOC_BUS_CLK_STG_AXI 96
+#define JH7110_GMAC5_CLK_AHB 97
+#define JH7110_GMAC5_CLK_AXI 98
+#define JH7110_GMAC_SRC 99
+#define JH7110_GMAC1_GTXCLK 100
+#define JH7110_GMAC1_RMII_RTX 101
+#define JH7110_GMAC5_CLK_PTP 102
+#define JH7110_GMAC5_CLK_RX 103
+#define JH7110_GMAC5_CLK_RX_INV 104
+#define JH7110_GMAC5_CLK_TX 105
+#define JH7110_GMAC5_CLK_TX_INV 106
+#define JH7110_GMAC1_GTXC 107
+#define JH7110_GMAC0_GTXCLK 108
+#define JH7110_GMAC0_PTP 109
+#define JH7110_GMAC_PHY 110
+#define JH7110_GMAC0_GTXC 111
+#define JH7110_SYS_IOMUX_PCLK 112
+#define JH7110_MAILBOX_CLK_APB 113
+#define JH7110_INT_CTRL_CLK_APB 114
+#define JH7110_CAN0_CTRL_CLK_APB 115
+#define JH7110_CAN0_CTRL_CLK_TIMER 116
+#define JH7110_CAN0_CTRL_CLK_CAN 117
+#define JH7110_CAN1_CTRL_CLK_APB 118
+#define JH7110_CAN1_CTRL_CLK_TIMER 119
+#define JH7110_CAN1_CTRL_CLK_CAN 120
+#define JH7110_PWM_CLK_APB 121
+#define JH7110_DSKIT_WDT_CLK_APB 122
+#define JH7110_DSKIT_WDT_CLK_WDT 123
+#define JH7110_TIMER_CLK_APB 124
+#define JH7110_TIMER_CLK_TIMER0 125
+#define JH7110_TIMER_CLK_TIMER1 126
+#define JH7110_TIMER_CLK_TIMER2 127
+#define JH7110_TIMER_CLK_TIMER3 128
+#define JH7110_TEMP_SENSOR_CLK_APB 129
+#define JH7110_TEMP_SENSOR_CLK_TEMP 130
+#define JH7110_SPI0_CLK_APB 131
+#define JH7110_SPI1_CLK_APB 132
+#define JH7110_SPI2_CLK_APB 133
+#define JH7110_SPI3_CLK_APB 134
+#define JH7110_SPI4_CLK_APB 135
+#define JH7110_SPI5_CLK_APB 136
+#define JH7110_SPI6_CLK_APB 137
+#define JH7110_I2C0_CLK_APB 138
+#define JH7110_I2C1_CLK_APB 139
+#define JH7110_I2C2_CLK_APB 140
+#define JH7110_I2C3_CLK_APB 141
+#define JH7110_I2C4_CLK_APB 142
+#define JH7110_I2C5_CLK_APB 143
+#define JH7110_I2C6_CLK_APB 144
+#define JH7110_UART0_CLK_APB 145
+#define JH7110_UART0_CLK_CORE 146
+#define JH7110_UART1_CLK_APB 147
+#define JH7110_UART1_CLK_CORE 148
+#define JH7110_UART2_CLK_APB 149
+#define JH7110_UART2_CLK_CORE 150
+#define JH7110_UART3_CLK_APB 151
+#define JH7110_UART3_CLK_CORE 152
+#define JH7110_UART4_CLK_APB 153
+#define JH7110_UART4_CLK_CORE 154
+#define JH7110_UART5_CLK_APB 155
+#define JH7110_UART5_CLK_CORE 156
+#define JH7110_PWMDAC_CLK_APB 157
+#define JH7110_PWMDAC_CLK_CORE 158
+#define JH7110_SPDIF_CLK_APB 159
+#define JH7110_SPDIF_CLK_CORE 160
+#define JH7110_I2STX0_4CHCLK_APB 161
+#define JH7110_I2STX_4CH0_BCLK_MST 162
+#define JH7110_I2STX_4CH0_BCLK_MST_INV 163
+#define JH7110_I2STX_4CH0_LRCK_MST 164
+#define JH7110_I2STX0_4CHBCLK 165
+#define JH7110_I2STX0_4CHBCLK_N 166
+#define JH7110_I2STX0_4CHLRCK 167
+#define JH7110_I2STX1_4CHCLK_APB 168
+#define JH7110_I2STX_4CH1_BCLK_MST 169
+#define JH7110_I2STX_4CH1_BCLK_MST_INV 170
+#define JH7110_I2STX_4CH1_LRCK_MST 171
+#define JH7110_I2STX1_4CHBCLK 172
+#define JH7110_I2STX1_4CHBCLK_N 173
+#define JH7110_I2STX1_4CHLRCK 174
+#define JH7110_I2SRX0_3CH_CLK_APB 175
+#define JH7110_I2SRX_3CH_BCLK_MST 176
+#define JH7110_I2SRX_3CH_BCLK_MST_INV 177
+#define JH7110_I2SRX_3CH_LRCK_MST 178
+#define JH7110_I2SRX0_3CH_BCLK 179
+#define JH7110_I2SRX0_3CH_BCLK_N 180
+#define JH7110_I2SRX0_3CH_LRCK 181
+#define JH7110_PDM_CLK_DMIC 182
+#define JH7110_PDM_CLK_APB 183
+#define JH7110_TDM_CLK_AHB 184
+#define JH7110_TDM_CLK_APB 185
+#define JH7110_TDM_INTERNAL 186
+#define JH7110_TDM_CLK_TDM 187
+#define JH7110_TDM_CLK_TDM_N 188
+#define JH7110_JTAG_CERTIFICATION_TRNG_CLK 189
+
+#define JH7110_CLK_SYS_REG_END 190
+
+/* stg regisger */
+#define JH7110_HIFI4_CLK_CORE 190
+#define JH7110_USB0_CLK_USB_APB 191
+#define JH7110_USB0_CLK_UTMI_APB 192
+#define JH7110_USB0_CLK_AXI 193
+#define JH7110_USB0_CLK_LPM 194
+#define JH7110_USB0_CLK_STB 195
+#define JH7110_USB0_CLK_APP_125 196
+#define JH7110_USB0_REFCLK 197
+#define JH7110_PCIE0_CLK_AXI_MST0 198
+#define JH7110_PCIE0_CLK_APB 199
+#define JH7110_PCIE0_CLK_TL 200
+#define JH7110_PCIE1_CLK_AXI_MST0 201
+#define JH7110_PCIE1_CLK_APB 202
+#define JH7110_PCIE1_CLK_TL 203
+#define JH7110_PCIE01_SLV_DEC_MAINCLK 204
+#define JH7110_SEC_HCLK 205
+#define JH7110_SEC_MISCAHB_CLK 206
+#define JH7110_STG_MTRX_GRP0_CLK_MAIN 207
+#define JH7110_STG_MTRX_GRP0_CLK_BUS 208
+#define JH7110_STG_MTRX_GRP0_CLK_STG 209
+#define JH7110_STG_MTRX_GRP1_CLK_MAIN 210
+#define JH7110_STG_MTRX_GRP1_CLK_BUS 211
+#define JH7110_STG_MTRX_GRP1_CLK_STG 212
+#define JH7110_STG_MTRX_GRP1_CLK_HIFI 213
+#define JH7110_E2_RTC_CLK 214
+#define JH7110_E2_CLK_CORE 215
+#define JH7110_E2_CLK_DBG 216
+#define JH7110_DMA1P_CLK_AXI 217
+#define JH7110_DMA1P_CLK_AHB 218
+
+#define JH7110_CLK_STG_REG_END 219
+
+/* aon regisger */
+#define JH7110_OSC_DIV4 219
+#define JH7110_AON_APB_FUNC 220
+#define JH7110_U0_GMAC5_CLK_AHB 221
+#define JH7110_U0_GMAC5_CLK_AXI 222
+#define JH7110_GMAC0_RMII_RTX 223
+#define JH7110_U0_GMAC5_CLK_TX 224
+#define JH7110_U0_GMAC5_CLK_TX_INV 225
+#define JH7110_U0_GMAC5_CLK_RX 226
+#define JH7110_U0_GMAC5_CLK_RX_INV 227
+#define JH7110_OTPC_CLK_APB 228
+#define JH7110_RTC_HMS_CLK_APB 229
+#define JH7110_RTC_INTERNAL 230
+#define JH7110_RTC_HMS_CLK_OSC32K 231
+#define JH7110_RTC_HMS_CLK_CAL 232
+
+#define JH7110_CLK_REG_END 233
+
+/* sys other */
+#define JH7110_PLL0_OUT 233
+#define JH7110_PLL1_OUT 234
+#define JH7110_PLL2_OUT 235
+#define JH7110_AON_APB 236
+#define JH7110_RESET1_CTRL_CLK_SRC 237
+#define JH7110_DDR_ROOT 238
+#define JH7110_VDEC_ROOT 239
+#define JH7110_VENC_ROOT 240
+#define JH7110_VOUT_ROOT 241
+#define JH7110_GMACUSB_ROOT 242
+#define JH7110_PCLK2_MUX_FUNC_PCLK 243
+#define JH7110_PCLK2_MUX_BIST_PCLK 244
+#define JH7110_APB_BUS 245
+#define JH7110_APB12 246
+#define JH7110_AXI_CFG1 247
+#define JH7110_PLL_WRAP_CRG_GCLK0 248
+#define JH7110_PLL_WRAP_CRG_GCLK1 249
+#define JH7110_PLL_WRAP_CRG_GCLK2 250
+#define JH7110_JTAG2APB_PCLK 251
+#define JH7110_U7_BUS_CLK 252
+#define JH7110_U7_IRQ_SYNC_BUS_CLK 253
+#define JH7110_NOC_BUS_CLK2_CPU_AXI 254
+#define JH7110_NOC_BUS_CLK_APB_BUS 255
+#define JH7110_NOC_BUS_CLK2_APB_BUS 256
+#define JH7110_NOC_BUS_CLK2_AXICFG0_AXI 257
+#define JH7110_DDR_CLK_DDRPHY_PLL_BYPASS 258
+#define JH7110_DDR_CLK_OSC 259
+#define JH7110_DDR_CLK_APB 260
+#define JH7110_NOC_BUS_CLK_DDRC 261
+#define JH7110_NOC_BUS_CLK2_DDRC 262
+#define JH7110_SYS_AHB_DEC_CLK_AHB 263
+#define JH7110_STG_AHB_DEC_CLK_AHB 264
+#define JH7110_NOC_BUS_CLK2_GPU_AXI 265
+#define JH7110_ISP_TOP_CLK_DVP 266
+#define JH7110_NOC_BUS_CLK2_ISP_AXI 267
+#define JH7110_ISP_TOP_CLK_BIST_APB 268
+#define JH7110_NOC_BUS_CLK2_DISP_AXI 269
+#define JH7110_VOUT_TOP_CLK_HDMITX0_BCLK 270
+#define JH7110_VOUT_TOP_U0_HDMI_TX_PIN_WS 271
+#define JH7110_VOUT_TOP_CLK_HDMIPHY_REF 272
+#define JH7110_VOUT_TOP_BIST_PCLK 273
+#define JH7110_AXIMEM0_128B_CLK_AXI 274
+#define JH7110_VDEC_INTSRAM_CLK_VDEC_AXI 275
+#define JH7110_NOC_BUS_CLK2_VDEC_AXI 276
+#define JH7110_AXIMEM1_128B_CLK_AXI 277
+#define JH7110_VENC_INTSRAM_CLK_VENC_AXI 278
+#define JH7110_NOC_BUS_CLK2_VENC_AXI 279
+#define JH7110_SRAM_CLK_ROM 280
+#define JH7110_NOC_BUS_CLK2_STG_AXI 281
+#define JH7110_GMAC5_CLK_RMII 282
+#define JH7110_AON_AHB 283
+#define JH7110_SYS_CRG_PCLK 284
+#define JH7110_SYS_SYSCON_PCLK 285
+#define JH7110_SPI0_CLK_CORE 286
+#define JH7110_SPI1_CLK_CORE 287
+#define JH7110_SPI2_CLK_CORE 288
+#define JH7110_SPI3_CLK_CORE 289
+#define JH7110_SPI4_CLK_CORE 290
+#define JH7110_SPI5_CLK_CORE 291
+#define JH7110_SPI6_CLK_CORE 292
+#define JH7110_I2C0_CLK_CORE 293
+#define JH7110_I2C1_CLK_CORE 294
+#define JH7110_I2C2_CLK_CORE 295
+#define JH7110_I2C3_CLK_CORE 296
+#define JH7110_I2C4_CLK_CORE 297
+#define JH7110_I2C5_CLK_CORE 298
+#define JH7110_I2C6_CLK_CORE 299
+#define JH7110_I2STX_BCLK_MST 300
+#define JH7110_I2STX_LRCK_MST 301
+#define JH7110_I2SRX_BCLK_MST 302
+#define JH7110_I2SRX_LRCK_MST 303
+#define JH7110_PDM_CLK_DMIC0_BCLK_SLV 304
+#define JH7110_PDM_CLK_DMIC0_LRCK_SLV 305
+#define JH7110_PDM_CLK_DMIC1_BCLK_SLV 306
+#define JH7110_PDM_CLK_DMIC1_LRCK_SLV 307
+#define JH7110_TDM_CLK_MST 308
+#define JH7110_AHB2APB_CLK_AHB 309
+#define JH7110_P2P_ASYNC_CLK_APBS 310
+#define JH7110_P2P_ASYNC_CLK_APBM 311
+#define JH7110_JTAG_DAISY_CHAIN_JTAG_TCK 312
+#define JH7110_U7_DEBUG_SYSTEMJTAG_JTAG_TCK 313
+#define JH7110_E2_DEBUG_SYSTEMJTAG_TCK 314
+#define JH7110_JTAG_CERTIFICATION_TCK 315
+#define JH7110_SEC_SKP_CLK 316
+#define JH7110_U2_PCLK_MUX_PCLK 317
+
+#define JH7110_CLK_SYS_END 318
+
+/* stg other */
+#define JH7110_PCIE0_CLK_AXI_SLV0 318
+#define JH7110_PCIE0_CLK_AXI_SLV 319
+#define JH7110_PCIE0_CLK_OSC 320
+#define JH7110_PCIE1_CLK_AXI_SLV0 321
+#define JH7110_PCIE1_CLK_AXI_SLV 322
+#define JH7110_PCIE1_CLK_OSC 323
+#define JH7110_E2_IRQ_SYNC_CLK_CORE 324
+#define JH7110_STG_CRG_PCLK 325
+#define JH7110_STG_SYSCON_PCLK 326
+
+#define JH7110_CLK_STG_END 327
+
+/* aon other */
+#define JH7110_U0_GMAC5_CLK_PTP 327
+#define JH7110_U0_GMAC5_CLK_RMII 328
+#define JH7110_AON_SYSCON_PCLK 329
+#define JH7110_AON_IOMUX_PCLK 330
+#define JH7110_AON_CRG_PCLK 331
+#define JH7110_PMU_CLK_APB 332
+#define JH7110_PMU_CLK_WKUP 333
+#define JH7110_RTC_HMS_CLK_OSC32K_G 334
+#define JH7110_32K_OUT 335
+#define JH7110_RESET0_CTRL_CLK_SRC 336
+/* aon other and source */
+#define JH7110_PCLK_MUX_FUNC_PCLK 337
+#define JH7110_PCLK_MUX_BIST_PCLK 338
+
+#define JH7110_CLK_END 339
+
+/* sys external clocks */
+#define JH7110_OSC (JH7110_CLK_END + 0)
+#define JH7110_GMAC1_RMII_REFIN (JH7110_CLK_END + 1)
+#define JH7110_GMAC1_RGMII_RXIN (JH7110_CLK_END + 2)
+#define JH7110_I2STX_BCLK_EXT (JH7110_CLK_END + 3)
+#define JH7110_I2STX_LRCK_EXT (JH7110_CLK_END + 4)
+#define JH7110_I2SRX_BCLK_EXT (JH7110_CLK_END + 5)
+#define JH7110_I2SRX_LRCK_EXT (JH7110_CLK_END + 6)
+#define JH7110_TDM_EXT (JH7110_CLK_END + 7)
+#define JH7110_MCLK_EXT (JH7110_CLK_END + 8)
+#define JH7110_JTAG_TCK_INNER (JH7110_CLK_END + 9)
+#define JH7110_BIST_APB (JH7110_CLK_END + 10)
+
+/* stg external clocks */
+#define JH7110_STG_APB (JH7110_CLK_END + 11)
+
+/* aon external clocks */
+#define JH7110_GMAC0_RMII_REFIN (JH7110_CLK_END + 12)
+#define JH7110_GMAC0_RGMII_RXIN (JH7110_CLK_END + 13)
+#define JH7110_CLK_RTC (JH7110_CLK_END + 14)
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
projects / platform / kernel / linux-starfive.git / commitdiff