+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
; PR1822
ret i32 %retval
}
+; FIXME - vector neglect
+define <2 x i32> @test68vec(<2 x i32> %x) {
+; CHECK-LABEL: @test68vec(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> %x, <i32 11, i32 11>
+; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> <i32 11, i32 11>, <2 x i32> %x
+; CHECK-NEXT: [[CMP3:%.*]] = icmp sgt <2 x i32> [[COND]], <i32 92, i32 92>
+; CHECK-NEXT: [[RETVAL:%.*]] = select <2 x i1> [[CMP3]], <2 x i32> <i32 92, i32 92>, <2 x i32> [[COND]]
+; CHECK-NEXT: ret <2 x i32> [[RETVAL]]
+;
+ %cmp = icmp slt <2 x i32> <i32 11, i32 11>, %x
+ %cond = select <2 x i1> %cmp, <2 x i32> <i32 11, i32 11>, <2 x i32> %x
+ %cmp3 = icmp slt <2 x i32> <i32 92, i32 92>, %cond
+ %retval = select <2 x i1> %cmp3, <2 x i32> <i32 92, i32 92>, <2 x i32> %cond
+ ret <2 x i32> %retval
+}
+
; MIN(MIN(X, 24), 83) -> MIN(X, 24)
define i32 @test69(i32 %x) {
; CHECK-LABEL: @test69(
ret i32 %retval
}
+; FIXME - vector neglect
+define <2 x i32> @test72vec(<2 x i32> %x) {
+; CHECK-LABEL: @test72vec(
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> %x, <i32 92, i32 92>
+; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> <i32 92, i32 92>, <2 x i32> %x
+; CHECK-NEXT: [[CMP3:%.*]] = icmp sgt <2 x i32> [[COND]], <i32 11, i32 11>
+; CHECK-NEXT: [[RETVAL:%.*]] = select <2 x i1> [[CMP3]], <2 x i32> <i32 11, i32 11>, <2 x i32> [[COND]]
+; CHECK-NEXT: ret <2 x i32> [[RETVAL]]
+;
+ %cmp = icmp sgt <2 x i32> %x, <i32 92, i32 92>
+ %cond = select <2 x i1> %cmp, <2 x i32> <i32 92, i32 92>, <2 x i32> %x
+ %cmp3 = icmp sgt <2 x i32> %cond, <i32 11, i32 11>
+ %retval = select <2 x i1> %cmp3, <2 x i32> <i32 11, i32 11>, <2 x i32> %cond
+ ret <2 x i32> %retval
+}
+
; MIN(MIN(X, 83), 24) -> MIN(X, 24)
define i32 @test73(i32 %x) {
; CHECK-LABEL: @test73(