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Remove the extra leading 0 from VMAXNMND.
author
Joey Gouly
<joey.gouly@arm.com>
Thu, 18 Jul 2013 09:34:35 +0000
(09:34 +0000)
committer
Joey Gouly
<joey.gouly@arm.com>
Thu, 18 Jul 2013 09:34:35 +0000
(09:34 +0000)
The N3VDIntnp pattern takes bits<5> and I gave it 6 bits.
Thanks to Jiangning Liu for spotting it!
llvm-svn: 186568
llvm/lib/Target/ARM/ARMInstrNEON.td
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diff --git
a/llvm/lib/Target/ARM/ARMInstrNEON.td
b/llvm/lib/Target/ARM/ARMInstrNEON.td
index
f349f10
..
f389909
100644
(file)
--- a/
llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/
llvm/lib/Target/ARM/ARMInstrNEON.td
@@
-4682,7
+4682,7
@@
def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
// VMAXNM
let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
- def VMAXNMND : N3VDIntnp<0b00
0
110, 0b00, 0b1111, 0, 1,
+ def VMAXNMND : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
N3RegFrm, NoItinerary, "vmaxnm", "f32",
v2f32, v2f32, int_arm_neon_vmaxnm, 1>,
Requires<[HasV8, HasNEON]>;