Convert CONFIG_SYS_FSL_CCSR_GUR_BE et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_FSL_CCSR_GUR_BE
   CONFIG_SYS_FSL_CCSR_SCFG_BE
   CONFIG_SYS_FSL_ESDHC_BE
   CONFIG_SYS_FSL_IFC_BE
   CONFIG_SYS_FSL_PEX_LUT_BE
   CONFIG_SYS_FSL_CCSR_GUR_LE
   CONFIG_SYS_FSL_CCSR_SCFG_LE
   CONFIG_SYS_FSL_ESDHC_LE
   CONFIG_SYS_FSL_IFC_LE
   CONFIG_SYS_FSL_PEX_LUT_LE

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index 70c99aa..7921682 100644 (file)
--- a/README
+++ b/README
@@ -396,12 +396,6 @@ The following options need to be configured:
                Board config to use DDR3L. It can be enabled for SoCs with
                DDR3L controllers.
 
-               CONFIG_SYS_FSL_IFC_BE
-               Defines the IFC controller register space as Big Endian
-
-               CONFIG_SYS_FSL_IFC_LE
-               Defines the IFC controller register space as Little Endian
-
                CONFIG_SYS_FSL_IFC_CLK_DIV
                Defines divider of platform clock(clock input to IFC controller).
 

diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index d3ebbff..a96245c 100644 (file)
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -227,6 +227,12 @@ config VOL_MONITOR_ISL68233_SET
 
 endif
 
+config SYS_FSL_ESDHC_BE
+       bool
+
+config SYS_FSL_IFC_BE
+       bool
+
 config FSL_QIXIS
        bool "Enable QIXIS support"
        depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index a901360..e75a895 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -3,6 +3,7 @@ config ARCH_LS1021A
        select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
        select SYS_FSL_DDR_BE if SYS_FSL_DDR
        select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+       select SYS_FSL_IFC_BE
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A008407
        select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
@@ -12,6 +13,7 @@ config ARCH_LS1021A
        select SYS_FSL_ERRATUM_A009798 if USB
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
+       select SYS_FSL_ESDHC_BE
        select SYS_FSL_HAS_CCI400
        select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
        select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 602b624..1f86070 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -323,6 +323,11 @@ config ARCH_LX2160A
 config FSL_LSCH2
        bool
        select SKIP_LOWLEVEL_INIT
+       select SYS_FSL_CCSR_GUR_BE
+       select SYS_FSL_CCSR_SCFG_BE
+       select SYS_FSL_ESDHC_BE
+       select SYS_FSL_IFC_BE
+       select SYS_FSL_PEX_LUT_BE
        select SYS_FSL_HAS_CCI400
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
@@ -330,11 +335,40 @@ config FSL_LSCH2
 
 config FSL_LSCH3
        select ARCH_MISC_INIT
+       select SYS_FSL_CCSR_GUR_LE
+       select SYS_FSL_CCSR_SCFG_LE
+       select SYS_FSL_ESDHC_LE
+       select SYS_FSL_IFC_LE
+       select SYS_FSL_PEX_LUT_LE
        bool
 
 config NXP_LSCH3_2
        bool
 
+config SYS_FSL_CCSR_GUR_BE
+       bool
+
+config SYS_FSL_CCSR_SCFG_BE
+       bool
+
+config SYS_FSL_PEX_LUT_BE
+       bool
+
+config SYS_FSL_CCSR_GUR_LE
+       bool
+
+config SYS_FSL_CCSR_SCFG_LE
+       bool
+
+config SYS_FSL_ESDHC_LE
+       bool
+
+config SYS_FSL_IFC_LE
+       bool
+
+config SYS_FSL_PEX_LUT_LE
+       bool
+
 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
 

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 9aee971..f6710d0 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -40,12 +40,6 @@
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
-#define CONFIG_SYS_FSL_CCSR_SCFG_LE
-#define CONFIG_SYS_FSL_ESDHC_LE
-#define CONFIG_SYS_FSL_IFC_LE
-#define CONFIG_SYS_FSL_PEX_LUT_LE
-
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 
 /* Generic Interrupt Controller Definitions */
@@ -56,7 +50,6 @@
 #define SMMU_BASE                      0x05000000 /* GR0 Base */
 
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
 
 /* Cache Coherent Interconnect */
 #define CCI_MN_BASE                    0x04000000
@@ -141,16 +134,9 @@
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
-#define CONFIG_SYS_FSL_CCSR_SCFG_LE
-#define CONFIG_SYS_FSL_ESDHC_LE
-#define CONFIG_SYS_FSL_IFC_LE
-#define CONFIG_SYS_FSL_PEX_LUT_LE
-
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE       0x00200000 /* 2M space */
@@ -179,11 +165,6 @@
 #define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
-#define CONFIG_SYS_FSL_CCSR_SCFG_LE
-#define CONFIG_SYS_FSL_ESDHC_LE
-#define CONFIG_SYS_FSL_PEX_LUT_LE
-
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 
 /* Generic Interrupt Controller Definitions */
@@ -194,7 +175,6 @@
 #define SMMU_BASE                              0x05000000 /* GR0 Base */
 
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 
@@ -234,18 +214,12 @@
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
-#define CONFIG_SYS_FSL_CCSR_SCFG_LE
-#define CONFIG_SYS_FSL_ESDHC_LE
-#define CONFIG_SYS_FSL_PEX_LUT_LE
-
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 
 /* SEC */
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
 
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
@@ -255,12 +229,8 @@
 #define DCSR_DCFG_SBEESR2                      0x20140534
 #define DCSR_DCFG_MBEESR2                      0x20140544
 
-#define CONFIG_SYS_FSL_CCSR_SCFG_BE
-#define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_CCSR_GUR_BE
-#define CONFIG_SYS_FSL_PEX_LUT_BE
 
 /* SoC related */
 #ifdef CONFIG_ARCH_LS1043A
@@ -275,8 +245,6 @@
 #define MAX_QE_RISC            1
 #define QE_NUM_OF_SNUM         28
 
-#define CONFIG_SYS_FSL_IFC_BE
-
 /* SMMU Defintions */
 #define SMMU_BASE              0x09000000
 
@@ -323,8 +291,6 @@
 #define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_IFC_BE
-
 /* SMMU Defintions */
 #define SMMU_BASE              0x09000000
 

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index e5f61ea..868456f 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -79,8 +79,6 @@
 #define CONFIG_MAX_MEM_MAPPED                  ((phys_size_t)2 << 30)
 #endif
 
-#define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
 

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 737bdd8..2cb5dae 100644 (file)
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -20,6 +20,7 @@ config MPC85xx
        select CREATE_ARCH_SYMLINK
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
+       select SYS_FSL_IFC_BE
        select BINMAN if OF_SEPARATE
        imply CMD_HASH
        imply CMD_IRQ

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 169c91c..d9909f5 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -16,9 +16,6 @@
 
 #include <fsl_ddrc_version.h>
 
-/* IP endianness */
-#define CONFIG_SYS_FSL_IFC_BE
-
 #if defined(CONFIG_ARCH_MPC8548)
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9