[RISCV] Codegen support for the standard RV32M instruction set extension

llvm-svn: 322843

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d5d23129ff9e4b64284e526816c172c8e945f793..40a9683e963351fa2ab99bdb7ba368b438ff432a 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -77,18 +77,20 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::SUBC, XLenVT, Expand);
   setOperationAction(ISD::SUBE, XLenVT, Expand);
 
-  setOperationAction(ISD::SREM, XLenVT, Expand);
+  if (!Subtarget.hasStdExtM()) {
+    setOperationAction(ISD::MUL, XLenVT, Expand);
+    setOperationAction(ISD::MULHS, XLenVT, Expand);
+    setOperationAction(ISD::MULHU, XLenVT, Expand);
+    setOperationAction(ISD::SDIV, XLenVT, Expand);
+    setOperationAction(ISD::UDIV, XLenVT, Expand);
+    setOperationAction(ISD::SREM, XLenVT, Expand);
+    setOperationAction(ISD::UREM, XLenVT, Expand);
+  }
+
   setOperationAction(ISD::SDIVREM, XLenVT, Expand);
-  setOperationAction(ISD::SDIV, XLenVT, Expand);
-  setOperationAction(ISD::UREM, XLenVT, Expand);
   setOperationAction(ISD::UDIVREM, XLenVT, Expand);
-  setOperationAction(ISD::UDIV, XLenVT, Expand);
-
-  setOperationAction(ISD::MUL, XLenVT, Expand);
   setOperationAction(ISD::SMUL_LOHI, XLenVT, Expand);
   setOperationAction(ISD::UMUL_LOHI, XLenVT, Expand);
-  setOperationAction(ISD::MULHS, XLenVT, Expand);
-  setOperationAction(ISD::MULHU, XLenVT, Expand);
 
   setOperationAction(ISD::SHL_PARTS, XLenVT, Expand);
   setOperationAction(ISD::SRL_PARTS, XLenVT, Expand);

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
index fec9c1f93997b3969addc69cfccf113af94e720a..2dd10ada4003eb80923d0b20e30c986c698fbe69 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
@@ -34,3 +34,18 @@ def DIVUW   : ALUW_rr<0b0000001, 0b101, "divuw">;
 def REMW    : ALUW_rr<0b0000001, 0b110, "remw">;
 def REMUW   : ALUW_rr<0b0000001, 0b111, "remuw">;
 } // Predicates = [HasStdExtM, IsRV64]
+
+//===----------------------------------------------------------------------===//
+// Pseudo-instructions and codegen patterns
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtM] in {
+def : PatGprGpr<mul, MUL>;
+def : PatGprGpr<mulhs, MULH>;
+def : PatGprGpr<mulhu, MULHU>;
+// No ISDOpcode for mulhsu
+def : PatGprGpr<sdiv, DIV>;
+def : PatGprGpr<udiv, DIVU>;
+def : PatGprGpr<srem, REM>;
+def : PatGprGpr<urem, REMU>;
+} // Predicates = [HasStdExtM]

diff --git a/llvm/test/CodeGen/RISCV/div.ll b/llvm/test/CodeGen/RISCV/div.ll
index ec2347f48b7398db19562851d19d98d36746a6a4..96484459ecc51dfc749506fcdc899411f0e48f29 100644 (file)
--- a/llvm/test/CodeGen/RISCV/div.ll
+++ b/llvm/test/CodeGen/RISCV/div.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IM %s
 
 define i32 @udiv(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: udiv:
@@ -13,6 +15,11 @@ define i32 @udiv(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: udiv:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    divu a0, a0, a1
+; RV32IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
 }
@@ -29,6 +36,14 @@ define i32 @udiv_constant(i32 %a) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: udiv_constant:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    lui a1, 838861
+; RV32IM-NEXT:    addi a1, a1, -819
+; RV32IM-NEXT:    mulhu a0, a0, a1
+; RV32IM-NEXT:    srli a0, a0, 2
+; RV32IM-NEXT:    ret
   %1 = udiv i32 %a, 5
   ret i32 %1
 }
@@ -38,6 +53,11 @@ define i32 @udiv_pow2(i32 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a0, a0, 3
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: udiv_pow2:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    srli a0, a0, 3
+; RV32IM-NEXT:    ret
   %1 = udiv i32 %a, 8
   ret i32 %1
 }
@@ -53,6 +73,17 @@ define i64 @udiv64(i64 %a, i64 %b) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: udiv64:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    addi sp, sp, -16
+; RV32IM-NEXT:    sw ra, 12(sp)
+; RV32IM-NEXT:    lui a4, %hi(__udivdi3)
+; RV32IM-NEXT:    addi a4, a4, %lo(__udivdi3)
+; RV32IM-NEXT:    jalr a4
+; RV32IM-NEXT:    lw ra, 12(sp)
+; RV32IM-NEXT:    addi sp, sp, 16
+; RV32IM-NEXT:    ret
   %1 = udiv i64 %a, %b
   ret i64 %1
 }
@@ -70,6 +101,19 @@ define i64 @udiv64_constant(i64 %a) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: udiv64_constant:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    addi sp, sp, -16
+; RV32IM-NEXT:    sw ra, 12(sp)
+; RV32IM-NEXT:    lui a2, %hi(__udivdi3)
+; RV32IM-NEXT:    addi a4, a2, %lo(__udivdi3)
+; RV32IM-NEXT:    addi a2, zero, 5
+; RV32IM-NEXT:    mv a3, zero
+; RV32IM-NEXT:    jalr a4
+; RV32IM-NEXT:    lw ra, 12(sp)
+; RV32IM-NEXT:    addi sp, sp, 16
+; RV32IM-NEXT:    ret
   %1 = udiv i64 %a, 5
   ret i64 %1
 }
@@ -85,6 +129,11 @@ define i32 @sdiv(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: sdiv:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    div a0, a0, a1
+; RV32IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
 }
@@ -101,6 +150,16 @@ define i32 @sdiv_constant(i32 %a) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: sdiv_constant:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    lui a1, 419430
+; RV32IM-NEXT:    addi a1, a1, 1639
+; RV32IM-NEXT:    mulh a0, a0, a1
+; RV32IM-NEXT:    srli a1, a0, 31
+; RV32IM-NEXT:    srai a0, a0, 1
+; RV32IM-NEXT:    add a0, a0, a1
+; RV32IM-NEXT:    ret
   %1 = sdiv i32 %a, 5
   ret i32 %1
 }
@@ -113,6 +172,14 @@ define i32 @sdiv_pow2(i32 %a) nounwind {
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    srai a0, a0, 3
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: sdiv_pow2:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    srai a1, a0, 31
+; RV32IM-NEXT:    srli a1, a1, 29
+; RV32IM-NEXT:    add a0, a0, a1
+; RV32IM-NEXT:    srai a0, a0, 3
+; RV32IM-NEXT:    ret
   %1 = sdiv i32 %a, 8
   ret i32 %1
 }
@@ -128,6 +195,17 @@ define i64 @sdiv64(i64 %a, i64 %b) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: sdiv64:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    addi sp, sp, -16
+; RV32IM-NEXT:    sw ra, 12(sp)
+; RV32IM-NEXT:    lui a4, %hi(__divdi3)
+; RV32IM-NEXT:    addi a4, a4, %lo(__divdi3)
+; RV32IM-NEXT:    jalr a4
+; RV32IM-NEXT:    lw ra, 12(sp)
+; RV32IM-NEXT:    addi sp, sp, 16
+; RV32IM-NEXT:    ret
   %1 = sdiv i64 %a, %b
   ret i64 %1
 }
@@ -145,6 +223,19 @@ define i64 @sdiv64_constant(i64 %a) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: sdiv64_constant:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    addi sp, sp, -16
+; RV32IM-NEXT:    sw ra, 12(sp)
+; RV32IM-NEXT:    lui a2, %hi(__divdi3)
+; RV32IM-NEXT:    addi a4, a2, %lo(__divdi3)
+; RV32IM-NEXT:    addi a2, zero, 5
+; RV32IM-NEXT:    mv a3, zero
+; RV32IM-NEXT:    jalr a4
+; RV32IM-NEXT:    lw ra, 12(sp)
+; RV32IM-NEXT:    addi sp, sp, 16
+; RV32IM-NEXT:    ret
   %1 = sdiv i64 %a, 5
   ret i64 %1
 }

diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll
index 2ef6165615e414ce1c4e84c05e873d925ea97684..e1b2f6f7c2ebf8881a19dfa5e1b97371ca191351 100644 (file)
--- a/llvm/test/CodeGen/RISCV/mul.ll
+++ b/llvm/test/CodeGen/RISCV/mul.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IM %s
 
 define i32 @square(i32 %a) nounwind {
 ; RV32I-LABEL: square:
@@ -14,6 +16,11 @@ define i32 @square(i32 %a) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: square:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    mul a0, a0, a0
+; RV32IM-NEXT:    ret
   %1 = mul i32 %a, %a
   ret i32 %1
 }
@@ -29,6 +36,11 @@ define i32 @mul(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: mul:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    mul a0, a0, a1
+; RV32IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
 }
@@ -45,6 +57,12 @@ define i32 @mul_constant(i32 %a) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: mul_constant:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    addi a1, zero, 5
+; RV32IM-NEXT:    mul a0, a0, a1
+; RV32IM-NEXT:    ret
   %1 = mul i32 %a, 5
   ret i32 %1
 }
@@ -54,6 +72,11 @@ define i32 @mul_pow2(i32 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 3
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: mul_pow2:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    slli a0, a0, 3
+; RV32IM-NEXT:    ret
   %1 = mul i32 %a, 8
   ret i32 %1
 }
@@ -69,6 +92,16 @@ define i64 @mul64(i64 %a, i64 %b) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: mul64:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    mul a3, a0, a3
+; RV32IM-NEXT:    mulhu a4, a0, a2
+; RV32IM-NEXT:    add a3, a4, a3
+; RV32IM-NEXT:    mul a1, a1, a2
+; RV32IM-NEXT:    add a1, a3, a1
+; RV32IM-NEXT:    mul a0, a0, a2
+; RV32IM-NEXT:    ret
   %1 = mul i64 %a, %b
   ret i64 %1
 }
@@ -86,6 +119,71 @@ define i64 @mul64_constant(i64 %a) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: mul64_constant:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    addi a2, zero, 5
+; RV32IM-NEXT:    mul a1, a1, a2
+; RV32IM-NEXT:    mulhu a3, a0, a2
+; RV32IM-NEXT:    add a1, a3, a1
+; RV32IM-NEXT:    mul a0, a0, a2
+; RV32IM-NEXT:    ret
   %1 = mul i64 %a, 5
   ret i64 %1
 }
+
+define i32 @mulhs(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: mulhs:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp)
+; RV32I-NEXT:    mv a2, a1
+; RV32I-NEXT:    lui a1, %hi(__muldi3)
+; RV32I-NEXT:    addi a4, a1, %lo(__muldi3)
+; RV32I-NEXT:    srai a1, a0, 31
+; RV32I-NEXT:    srai a3, a2, 31
+; RV32I-NEXT:    jalr a4
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    lw ra, 12(sp)
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: mulhs:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    mulh a0, a0, a1
+; RV32IM-NEXT:    ret
+  %1 = sext i32 %a to i64
+  %2 = sext i32 %b to i64
+  %3 = mul i64 %1, %2
+  %4 = lshr i64 %3, 32
+  %5 = trunc i64 %4 to i32
+  ret i32 %5
+}
+
+define i32 @mulhu(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: mulhu:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp)
+; RV32I-NEXT:    mv a2, a1
+; RV32I-NEXT:    lui a1, %hi(__muldi3)
+; RV32I-NEXT:    addi a4, a1, %lo(__muldi3)
+; RV32I-NEXT:    mv a1, zero
+; RV32I-NEXT:    mv a3, zero
+; RV32I-NEXT:    jalr a4
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    lw ra, 12(sp)
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: mulhu:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    mulhu a0, a0, a1
+; RV32IM-NEXT:    ret
+  %1 = zext i32 %a to i64
+  %2 = zext i32 %b to i64
+  %3 = mul i64 %1, %2
+  %4 = lshr i64 %3, 32
+  %5 = trunc i64 %4 to i32
+  ret i32 %5
+}

diff --git a/llvm/test/CodeGen/RISCV/rem.ll b/llvm/test/CodeGen/RISCV/rem.ll
index 21737c93a80ba5c11a7e581a0ef22aab786dca5c..f9ef4c9c8e63aaa3b8ebd2be73d06a1c9251e92d 100644 (file)
--- a/llvm/test/CodeGen/RISCV/rem.ll
+++ b/llvm/test/CodeGen/RISCV/rem.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IM %s
 
 define i32 @urem(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: urem:
@@ -13,6 +15,11 @@ define i32 @urem(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: urem:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    remu a0, a0, a1
+; RV32IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
 }
@@ -28,6 +35,11 @@ define i32 @srem(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32IM-LABEL: srem:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    rem a0, a0, a1
+; RV32IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
 }