arm64: dts: mediatek: add ethernet support for mt8365 SoC
authorAlexandre Mergnat <amergnat@baylibre.com>
Wed, 29 Mar 2023 08:54:33 +0000 (10:54 +0200)
committerMatthias Brugger <matthias.bgg@gmail.com>
Thu, 30 Mar 2023 17:31:18 +0000 (19:31 +0200)
This IP is a 10/100 MAC controller compliant with IEEE 802.3 standards.
It supports power management with Energy Efficient Ethernet and Wake-on-LAN
specification. Flow control is provided for half-duplex and full-duplex
mode. For packet transmission and reception, the controller supports
IPv4/UDP/TCP checksum offload and VLAN tag insertion.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-12-0003e80e0095@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arch/arm64/boot/dts/mediatek/mt8365.dtsi

index 2a56997..1f6b483 100644 (file)
                        status = "disabled";
                };
 
+               ethernet: ethernet@112a0000 {
+                       compatible = "mediatek,mt8365-eth";
+                       reg = <0 0x112a0000 0 0x1000>;
+                       mediatek,pericfg = <&infracfg>;
+                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&topckgen CLK_TOP_ETH_SEL>,
+                                <&infracfg CLK_IFR_NIC_AXI>,
+                                <&infracfg CLK_IFR_NIC_SLV_AXI>;
+                       clock-names = "core", "reg", "trans";
+                       status = "disabled";
+               };
+
                u3phy: t-phy@11cc0000 {
                        compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
                        #address-cells = <1>;