intel/compiler: Track latency/perf of LSC fences

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11759>

diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp
index d4a0a87..edec07a 100644 (file)
--- a/src/intel/compiler/brw_ir_performance.cpp
+++ b/src/intel/compiler/brw_ir_performance.cpp
@@ -1106,6 +1106,7 @@ namespace {
                                      10 /* XXX */, 100 /* XXX */, 0, 0,
                                      0, 0);
 
+            case LSC_OP_FENCE:
             case LSC_OP_ATOMIC_INC:
             case LSC_OP_ATOMIC_DEC:
             case LSC_OP_ATOMIC_LOAD:

diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp
index 797c209..e19a9e5 100644 (file)
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -538,6 +538,7 @@ schedule_node::set_latency_gfx7(bool is_haswell)
          case LSC_OP_STORE_CMASK:
             latency = 300;
             break;
+         case LSC_OP_FENCE:
          case LSC_OP_ATOMIC_INC:
          case LSC_OP_ATOMIC_DEC:
          case LSC_OP_ATOMIC_LOAD: