/// be used with SelectionDAG::getMemIntrinsicNode.
static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END + 500;
+/// Get underlying scalar opcode for VECREDUCE opcode.
+/// For example ISD::AND for ISD::VECREDUCE_AND.
+NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode);
+
//===--------------------------------------------------------------------===//
/// MemIndexedMode enum - This enum defines the load / store indexed
/// addressing modes.
EVT LoOpVT, HiOpVT;
std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(VecVT);
- unsigned CombineOpc = 0;
- switch (N->getOpcode()) {
- case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break;
- case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break;
- case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break;
- case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break;
- case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break;
- case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break;
- case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break;
- case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break;
- case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break;
- case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
- case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
- case ISD::VECREDUCE_FMAX: CombineOpc = ISD::FMAXNUM; break;
- case ISD::VECREDUCE_FMIN: CombineOpc = ISD::FMINNUM; break;
- default:
- llvm_unreachable("Unexpected reduce ISD node");
- }
-
// Use the appropriate scalar instruction on the split subvectors before
// reducing the now partially reduced smaller vector.
+ unsigned CombineOpc = ISD::getVecReduceBaseOpcode(N->getOpcode());
SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags());
return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags());
}
return true;
}
+ISD::NodeType ISD::getVecReduceBaseOpcode(unsigned VecReduceOpcode) {
+ switch (VecReduceOpcode) {
+ default:
+ llvm_unreachable("Expected VECREDUCE opcode");
+ case ISD::VECREDUCE_FADD:
+ return ISD::FADD;
+ case ISD::VECREDUCE_FMUL:
+ return ISD::FMUL;
+ case ISD::VECREDUCE_ADD:
+ return ISD::ADD;
+ case ISD::VECREDUCE_MUL:
+ return ISD::MUL;
+ case ISD::VECREDUCE_AND:
+ return ISD::AND;
+ case ISD::VECREDUCE_OR:
+ return ISD::OR;
+ case ISD::VECREDUCE_XOR:
+ return ISD::XOR;
+ case ISD::VECREDUCE_SMAX:
+ return ISD::SMAX;
+ case ISD::VECREDUCE_SMIN:
+ return ISD::SMIN;
+ case ISD::VECREDUCE_UMAX:
+ return ISD::UMAX;
+ case ISD::VECREDUCE_UMIN:
+ return ISD::UMIN;
+ case ISD::VECREDUCE_FMAX:
+ return ISD::FMAXNUM;
+ case ISD::VECREDUCE_FMIN:
+ return ISD::FMINNUM;
+ }
+}
+
ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) {
switch (ExtType) {
case ISD::EXTLOAD:
SDValue TargetLowering::expandVecReduce(SDNode *Node, SelectionDAG &DAG) const {
SDLoc dl(Node);
- unsigned BaseOpcode = 0;
- switch (Node->getOpcode()) {
- default: llvm_unreachable("Expected VECREDUCE opcode");
- case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break;
- case ISD::VECREDUCE_FMUL: BaseOpcode = ISD::FMUL; break;
- case ISD::VECREDUCE_ADD: BaseOpcode = ISD::ADD; break;
- case ISD::VECREDUCE_MUL: BaseOpcode = ISD::MUL; break;
- case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break;
- case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break;
- case ISD::VECREDUCE_XOR: BaseOpcode = ISD::XOR; break;
- case ISD::VECREDUCE_SMAX: BaseOpcode = ISD::SMAX; break;
- case ISD::VECREDUCE_SMIN: BaseOpcode = ISD::SMIN; break;
- case ISD::VECREDUCE_UMAX: BaseOpcode = ISD::UMAX; break;
- case ISD::VECREDUCE_UMIN: BaseOpcode = ISD::UMIN; break;
- case ISD::VECREDUCE_FMAX: BaseOpcode = ISD::FMAXNUM; break;
- case ISD::VECREDUCE_FMIN: BaseOpcode = ISD::FMINNUM; break;
- }
-
+ unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Node->getOpcode());
SDValue Op = Node->getOperand(0);
EVT VT = Op.getValueType();