drm/amd/display: Update panel register

[Why]
Incorrect panel register settings are
applied for power sequence because the
register macro is not defined in resource.

[How]
Implement same register space to future
resource files.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index c4ffed9..2345f12 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -967,7 +967,7 @@ static const struct encoder_feature_support link_enc_feature = {
                [id] = {\
                                LE_DCN3_REG_LIST(id), \
                                UNIPHY_DCN2_REG_LIST(phyid), \
-                               DPCS_DCN2_REG_LIST(id), \
+                               SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
                }
 
 static const struct dcn10_link_enc_registers link_enc_regs[] = {