ARM: dts: exynos: add prefetch properties for L2C-310 cache

Add the devicetree properties to enable instruction and data prefetch
on exynos4210 and exynos4412 which use the L2C-310 cache.  No other
Exynos chip appears to be using this L2 cache hardware.

This follows the default bits being set in the l2c_aux_val register
for the Exynos platform, which can now be cleared as a result.

Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 33435ce79ce4c2c8611a458bd78efaa1837ca1c4..73360f29d53e89878de68337f017f33fa1455727 100644 (file)
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -102,6 +102,8 @@
                        reg = <0x10502000 0x1000>;
                        cache-unified;
                        cache-level = <2>;
+                       prefetch-data = <1>;
+                       prefetch-instr = <1>;
                        arm,tag-latency = <2 2 1>;
                        arm,data-latency = <2 2 1>;
                };

diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 7002832eb4c07a751e857482fb5990e3c94659d1..c74b1be12671bde5d56658944673d8aa339f206b 100644 (file)
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -218,6 +218,8 @@
                        reg = <0x10502000 0x1000>;
                        cache-unified;
                        cache-level = <2>;
+                       prefetch-data = <1>;
+                       prefetch-instr = <1>;
                        arm,tag-latency = <2 2 1>;
                        arm,data-latency = <3 2 1>;
                        arm,double-linefill = <1>;