EDAC/sifive: Add EDAC platform driver for SiFive SoCs
authorYash Shah <yash.shah@sifive.com>
Mon, 6 May 2019 11:27:06 +0000 (16:57 +0530)
committerTony Luck <tony.luck@intel.com>
Thu, 20 Jun 2019 18:44:36 +0000 (11:44 -0700)
Add an EDAC driver for SiFive SoCs. The initial version supports ECC
event monitoring and reporting through the EDAC framework for the SiFive
L2 cache controller. It registers for notifier events from the L2 cache
controller driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events.

 [ bp: Massage commit message. ]

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: James Morse <james.morse@arm.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: linux-riscv@lists.infradead.org
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: "Paul E. McKenney" <paulmck@linux.ibm.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: sachin.ghadi@sifive.com
Link: https://lkml.kernel.org/r/1557142026-15949-2-git-send-email-yash.shah@sifive.com
MAINTAINERS
arch/riscv/Kconfig
drivers/edac/Kconfig
drivers/edac/Makefile
drivers/edac/sifive_edac.c [new file with mode: 0644]

index 57f496c..046596f 100644 (file)
@@ -5809,6 +5809,12 @@ L:       linux-edac@vger.kernel.org
 S:     Maintained
 F:     drivers/edac/sb_edac.c
 
+EDAC-SIFIVE
+M:     Yash Shah <yash.shah@sifive.com>
+L:     linux-edac@vger.kernel.org
+S:     Supported
+F:     drivers/edac/sifive_edac.c
+
 EDAC-SKYLAKE
 M:     Tony Luck <tony.luck@intel.com>
 L:     linux-edac@vger.kernel.org
index 0c4b122..4961dea 100644 (file)
@@ -50,6 +50,7 @@ config RISCV
        select ARCH_HAS_PTE_SPECIAL
        select ARCH_HAS_MMIOWB
        select HAVE_EBPF_JIT if 64BIT
+       select EDAC_SUPPORT
 
 config MMU
        def_bool y
index 5e2e034..200c04c 100644 (file)
@@ -460,6 +460,12 @@ config EDAC_ALTERA_SDMMC
          Support for error detection and correction on the
          Altera SDMMC FIFO Memory for Altera SoCs.
 
+config EDAC_SIFIVE
+       bool "Sifive platform EDAC driver"
+       depends on EDAC=y && RISCV
+       help
+         Support for error detection and correction on the SiFive SoCs.
+
 config EDAC_SYNOPSYS
        tristate "Synopsys DDR Memory Controller"
        depends on ARCH_ZYNQ || ARCH_ZYNQMP
index 89ad4a8..165ca65 100644 (file)
@@ -79,6 +79,7 @@ obj-$(CONFIG_EDAC_OCTEON_PCI)         += octeon_edac-pci.o
 obj-$(CONFIG_EDAC_THUNDERX)            += thunderx_edac.o
 
 obj-$(CONFIG_EDAC_ALTERA)              += altera_edac.o
+obj-$(CONFIG_EDAC_SIFIVE)              += sifive_edac.o
 obj-$(CONFIG_EDAC_SYNOPSYS)            += synopsys_edac.o
 obj-$(CONFIG_EDAC_XGENE)               += xgene_edac.o
 obj-$(CONFIG_EDAC_TI)                  += ti_edac.o
diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
new file mode 100644 (file)
index 0000000..413cdb4
--- /dev/null
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SiFive Platform EDAC Driver
+ *
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ *
+ * This driver is partially based on octeon_edac-pc.c
+ *
+ */
+#include <linux/edac.h>
+#include <linux/platform_device.h>
+#include "edac_module.h"
+#include <asm/sifive_l2_cache.h>
+
+#define DRVNAME "sifive_edac"
+
+struct sifive_edac_priv {
+       struct notifier_block notifier;
+       struct edac_device_ctl_info *dci;
+};
+
+/**
+ * EDAC error callback
+ *
+ * @event: non-zero if unrecoverable.
+ */
+static
+int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+       const char *msg = (char *)ptr;
+       struct sifive_edac_priv *p;
+
+       p = container_of(this, struct sifive_edac_priv, notifier);
+
+       if (event == SIFIVE_L2_ERR_TYPE_UE)
+               edac_device_handle_ue(p->dci, 0, 0, msg);
+       else if (event == SIFIVE_L2_ERR_TYPE_CE)
+               edac_device_handle_ce(p->dci, 0, 0, msg);
+
+       return NOTIFY_OK;
+}
+
+static int ecc_register(struct platform_device *pdev)
+{
+       struct sifive_edac_priv *p;
+
+       p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
+       if (!p)
+               return -ENOMEM;
+
+       p->notifier.notifier_call = ecc_err_event;
+       platform_set_drvdata(pdev, p);
+
+       p->dci = edac_device_alloc_ctl_info(0, "sifive_ecc", 1, "sifive_ecc",
+                                           1, 1, NULL, 0,
+                                           edac_device_alloc_index());
+       if (IS_ERR(p->dci))
+               return PTR_ERR(p->dci);
+
+       p->dci->dev = &pdev->dev;
+       p->dci->mod_name = "Sifive ECC Manager";
+       p->dci->ctl_name = dev_name(&pdev->dev);
+       p->dci->dev_name = dev_name(&pdev->dev);
+
+       if (edac_device_add_device(p->dci)) {
+               dev_err(p->dci->dev, "failed to register with EDAC core\n");
+               goto err;
+       }
+
+       register_sifive_l2_error_notifier(&p->notifier);
+
+       return 0;
+
+err:
+       edac_device_free_ctl_info(p->dci);
+
+       return -ENXIO;
+}
+
+static int ecc_unregister(struct platform_device *pdev)
+{
+       struct sifive_edac_priv *p = platform_get_drvdata(pdev);
+
+       unregister_sifive_l2_error_notifier(&p->notifier);
+       edac_device_del_device(&pdev->dev);
+       edac_device_free_ctl_info(p->dci);
+
+       return 0;
+}
+
+static struct platform_device *sifive_pdev;
+
+static int __init sifive_edac_init(void)
+{
+       int ret;
+
+       sifive_pdev = platform_device_register_simple(DRVNAME, 0, NULL, 0);
+       if (IS_ERR(sifive_pdev))
+               return PTR_ERR(sifive_pdev);
+
+       ret = ecc_register(sifive_pdev);
+       if (ret)
+               platform_device_unregister(sifive_pdev);
+
+       return ret;
+}
+
+static void __exit sifive_edac_exit(void)
+{
+       ecc_unregister(sifive_pdev);
+       platform_device_unregister(sifive_pdev);
+}
+
+module_init(sifive_edac_init);
+module_exit(sifive_edac_exit);
+
+MODULE_AUTHOR("SiFive Inc.");
+MODULE_DESCRIPTION("SiFive platform EDAC driver");
+MODULE_LICENSE("GPL v2");