[InstCombine] add tests for icmp with bitmask logic op; NFC

diff --git a/llvm/test/Transforms/InstCombine/icmp-or.ll b/llvm/test/Transforms/InstCombine/icmp-or.ll
new file mode 100644 (file)
index 0000000..5fd19ed
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/icmp-or.ll
@@ -0,0 +1,111 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i1 @set_low_bit_mask_eq(i8 %x) {
+; CHECK-LABEL: @set_low_bit_mask_eq(
+; CHECK-NEXT:    [[SUB:%.*]] = or i8 [[X:%.*]], 1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[SUB]], 19
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %sub = or i8 %x, 1
+  %cmp = icmp eq i8 %sub, 19
+  ret i1 %cmp
+}
+
+define <2 x i1> @set_low_bit_mask_ne(<2 x i8> %x) {
+; CHECK-LABEL: @set_low_bit_mask_ne(
+; CHECK-NEXT:    [[SUB:%.*]] = or <2 x i8> [[X:%.*]], <i8 3, i8 3>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ne <2 x i8> [[SUB]], <i8 19, i8 19>
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+  %sub = or <2 x i8> %x, <i8 3, i8 3>
+  %cmp = icmp ne <2 x i8> %sub, <i8 19, i8 19>
+  ret <2 x i1> %cmp
+}
+
+define i1 @set_low_bit_mask_ugt(i8 %x) {
+; CHECK-LABEL: @set_low_bit_mask_ugt(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[X:%.*]], 19
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %sub = or i8 %x, 3
+  %cmp = icmp ugt i8 %sub, 19
+  ret i1 %cmp
+}
+
+define i1 @set_low_bit_mask_ult(i8 %x) {
+; CHECK-LABEL: @set_low_bit_mask_ult(
+; CHECK-NEXT:    [[SUB:%.*]] = or i8 [[X:%.*]], 3
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[SUB]], 19
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %sub = or i8 %x, 3
+  %cmp = icmp ult i8 %sub, 19
+  ret i1 %cmp
+}
+
+define i1 @set_low_bit_mask_uge(i8 %x) {
+; CHECK-LABEL: @set_low_bit_mask_uge(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i8 [[X:%.*]], 19
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %sub = or i8 %x, 3
+  %cmp = icmp uge i8 %sub, 20
+  ret i1 %cmp
+}
+
+define i1 @set_low_bit_mask_ule(i8 %x) {
+; CHECK-LABEL: @set_low_bit_mask_ule(
+; CHECK-NEXT:    [[SUB:%.*]] = or i8 [[X:%.*]], 3
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[SUB]], 19
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %sub = or i8 %x, 3
+  %cmp = icmp ule i8 %sub, 18
+  ret i1 %cmp
+}
+
+define i1 @set_low_bit_mask_sgt(i8 %x) {
+; CHECK-LABEL: @set_low_bit_mask_sgt(
+; CHECK-NEXT:    [[SUB:%.*]] = or i8 [[X:%.*]], 3
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[SUB]], 20
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %sub = or i8 %x, 3
+  %cmp = icmp sgt i8 %sub, 20
+  ret i1 %cmp
+}
+
+define i1 @set_low_bit_mask_slt(i8 %x) {
+; CHECK-LABEL: @set_low_bit_mask_slt(
+; CHECK-NEXT:    [[SUB:%.*]] = or i8 [[X:%.*]], 15
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[SUB]], 19
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %sub = or i8 %x, 15
+  %cmp = icmp slt i8 %sub, 19
+  ret i1 %cmp
+}
+
+define i1 @set_low_bit_mask_sge(i8 %x) {
+; CHECK-LABEL: @set_low_bit_mask_sge(
+; CHECK-NEXT:    [[SUB:%.*]] = or i8 [[X:%.*]], 31
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[SUB]], 50
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %sub = or i8 %x, 31
+  %cmp = icmp sge i8 %sub, 51
+  ret i1 %cmp
+}
+
+define i1 @set_low_bit_mask_sle(i8 %x) {
+; CHECK-LABEL: @set_low_bit_mask_sle(
+; CHECK-NEXT:    [[SUB:%.*]] = or i8 [[X:%.*]], 63
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[SUB]], 69
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %sub = or i8 %x, 63
+  %cmp = icmp sle i8 %sub, 68
+  ret i1 %cmp
+}
+