clk: tegra: pll: Add pre/post rate-change hooks

There is a need to temporarily re-parent CCLK away from PLLX if PLLX's
rate is about to change. The newly introduced PLL pre/post rate-change
hooks allow to handle such case.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 531c2b3..0b212cf 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -744,13 +744,19 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 
        state = clk_pll_is_enabled(hw);
 
+       if (state && pll->params->pre_rate_change) {
+               ret = pll->params->pre_rate_change();
+               if (WARN_ON(ret))
+                       return ret;
+       }
+
        _get_pll_mnp(pll, &old_cfg);
 
        if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
                        (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
                ret = pll->params->dyn_ramp(pll, cfg);
                if (!ret)
-                       return 0;
+                       goto done;
        }
 
        if (state) {
@@ -772,6 +778,10 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
                pll_clk_start_ss(pll);
        }
 
+done:
+       if (state && pll->params->post_rate_change)
+               pll->params->post_rate_change();
+
        return ret;
 }
 

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 659c0be..87a6fb2 100644 (file)
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -266,6 +266,10 @@ struct tegra_clk_pll;
  *                             disabled.
  * @dyn_ramp:                  Callback which can be used to define a custom
  *                             dynamic ramp function for a given PLL.
+ * @pre_rate_change:           Callback which is invoked just before changing
+ *                             PLL's rate.
+ * @post_rate_change:          Callback which is invoked right after changing
+ *                             PLL's rate.
  *
  * Flags:
  * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
@@ -342,6 +346,8 @@ struct tegra_clk_pll_params {
        void    (*set_defaults)(struct tegra_clk_pll *pll);
        int     (*dyn_ramp)(struct tegra_clk_pll *pll,
                        struct tegra_clk_pll_freq_table *cfg);
+       int     (*pre_rate_change)(void);
+       void    (*post_rate_change)(void);
 };
 
 #define TEGRA_PLL_USE_LOCK BIT(0)