tm2: make emmc run high speed [1/1]
authorruixuan.li <ruixuan.li@amlogic.com>
Mon, 1 Apr 2019 06:12:07 +0000 (14:12 +0800)
committerJianxiong Pan <jianxiong.pan@amlogic.com>
Thu, 11 Apr 2019 02:59:29 +0000 (10:59 +0800)
PD#SWPL-5658

Problem:
emmc run hs200 report cmd18 rx data crc

Solution:
emmc run high speed first

Verify:
passed on t962e2_ab319

Change-Id: Iaeef33e38f7c5130ebfd0e7c5886459b8138a803
Signed-off-by: ruixuan.li <ruixuan.li@amlogic.com>
arch/arm/boot/dts/amlogic/mesontm2.dtsi
arch/arm/boot/dts/amlogic/tm2_pxp.dts
arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
arch/arm64/boot/dts/amlogic/mesontm2.dtsi
arch/arm64/boot/dts/amlogic/tm2_pxp.dts
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
drivers/amlogic/mmc/aml_sd_emmc.c
include/linux/amlogic/sd.h

index 3c36336..96ef7e1 100644 (file)
 
        sd_emmc_c: emmc@ffe07000 {
                status = "disabled";
-               compatible = "amlogic, meson-mmc-tl1";
+               compatible = "amlogic, meson-mmc-tm2";
                reg = <0xffe07000 0x800>;
                interrupts = <0 191 1>;
                pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
                clocks = <&clkc CLKID_SD_EMMC_C>,
                           <&clkc CLKID_SD_EMMC_C_P0_COMP>,
                           <&clkc CLKID_FCLK_DIV2>,
-                          <&clkc CLKID_FCLK_DIV5>,
+                          <&clkc CLKID_FCLK_DIV2P5>,
                           <&clkc CLKID_GP0_PLL>,
                           <&xtal>;
                clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";
index f6c072b..8ffbf10 100644 (file)
 };  /* end of pinctrl_aobus */
 
 &sd_emmc_b {
-       status = "disabled";
+       status = "okay";
        sd {
                caps = "MMC_CAP_4_BIT_DATA",
                        "MMC_CAP_MMC_HIGHSPEED",
index 6f69409..3d7c79d 100644 (file)
                         "MMC_CAP_ERASE",
                         "MMC_CAP_CMD23",
                         "MMC_CAP_DRIVER_TYPE_D";
-               caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
+               //caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <198000000>;
+               f_max = <50000000>;
        };
 };
 
index 65240dd..6646cee 100644 (file)
                         "MMC_CAP_MMC_HIGHSPEED",
                         "MMC_CAP_SD_HIGHSPEED",
                         "MMC_CAP_NONREMOVABLE",
-                        "MMC_CAP_1_8V_DDR",
+                        /*"MMC_CAP_1_8V_DDR",*/
                         "MMC_CAP_HW_RESET",
                         "MMC_CAP_ERASE",
                         "MMC_CAP_CMD23";
-               caps2 = "MMC_CAP2_HS200";
+               //caps2 = "MMC_CAP2_HS200";
                /* "MMC_CAP2_HS400";*/
                f_min = <400000>;
-               f_max = <200000000>;
+               f_max = <50000000>;
        };
 };
 
index e8a7c8a..9debff2 100644 (file)
 
        sd_emmc_c: emmc@ffe07000 {
                status = "disabled";
-               compatible = "amlogic, meson-mmc-tl1";
+               compatible = "amlogic, meson-mmc-tm2";
                reg = <0x0 0xffe07000 0x0 0x800>;
                interrupts = <0 191 1>;
                pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
                clocks = <&clkc CLKID_SD_EMMC_C>,
                           <&clkc CLKID_SD_EMMC_C_P0_COMP>,
                           <&clkc CLKID_FCLK_DIV2>,
-                          <&clkc CLKID_FCLK_DIV5>,
+                          <&clkc CLKID_FCLK_DIV2P5>,
                           <&clkc CLKID_GP0_PLL>,
                           <&xtal>;
                clock-names = "core","clkin0","clkin1","clkin2","clkin3","xtal";
index 07e24ae..233ef24 100644 (file)
 };  /* end of pinctrl_aobus */
 
 &sd_emmc_b {
-       status = "disabled";
+       status = "okay";
        sd {
                caps = "MMC_CAP_4_BIT_DATA",
                        "MMC_CAP_MMC_HIGHSPEED",
index c6163e3..6c68b86 100644 (file)
                         "MMC_CAP_ERASE",
                         "MMC_CAP_CMD23",
                         "MMC_CAP_DRIVER_TYPE_D";
-               caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
+               //caps2 = "MMC_CAP2_HS200"; /* "MMC_CAP2_HS400";*/
                f_min = <400000>;
-               f_max = <198000000>;
+               f_max = <50000000>;
        };
 };
 
index 375bb38..26ef579 100644 (file)
 
        sd_emmc_b: sd@ffe05000 {
                status = "okay";
-               compatible = "amlogic, meson-mmc-tl1";
+               compatible = "amlogic, meson-mmc-tm2";
                reg = <0x0 0xffe05000 0x0 0x800>;
                interrupts = <0 190 1>;
 
                         "MMC_CAP_MMC_HIGHSPEED",
                         "MMC_CAP_SD_HIGHSPEED",
                         "MMC_CAP_NONREMOVABLE",
-                        "MMC_CAP_1_8V_DDR",
+                        /*"MMC_CAP_1_8V_DDR",*/
                         "MMC_CAP_HW_RESET",
                         "MMC_CAP_ERASE",
                         "MMC_CAP_CMD23";
-               caps2 = "MMC_CAP2_HS200";
-               /* "MMC_CAP2_HS400";*/
+               /*caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";*/
                f_min = <400000>;
-               f_max = <200000000>;
+               f_max = <50000000>;
        };
 };
 
index f814ba5..4c009bb 100644 (file)
@@ -3648,6 +3648,29 @@ static struct meson_mmc_data mmc_data_sm1 = {
        .sdmmc.sdr104.core_phase = 2,
        .sdmmc.sdr104.tx_phase = 0,
 };
+
+static struct meson_mmc_data mmc_data_tm2 = {
+       .chip_type = MMC_CHIP_TM2,
+       .port_a_base = 0xffe03000,
+       .port_b_base = 0xffe05000,
+       .port_c_base = 0xffe07000,
+       .pinmux_base = 0xff634400,
+       .clksrc_base = 0xff63c000,
+       .ds_pin_poll = 0x3a,
+       .ds_pin_poll_en = 0x48,
+       .ds_pin_poll_bit = 13,
+       .sdmmc.init.core_phase = 3,
+       .sdmmc.init.tx_phase = 0,
+       .sdmmc.init.rx_phase = 0,
+       .sdmmc.hs.core_phase = 3,
+       .sdmmc.ddr.core_phase = 2,
+       .sdmmc.hs2.core_phase = 2,
+       .sdmmc.hs4.core_phase = 0,
+       .sdmmc.hs4.tx_delay = 16,
+       .sdmmc.sd_hs.core_phase = 2,
+       .sdmmc.sdr104.core_phase = 2,
+};
+
 static const struct of_device_id meson_mmc_of_match[] = {
        {
                .compatible = "amlogic, meson-mmc-gxbb",
@@ -3705,6 +3728,10 @@ static const struct of_device_id meson_mmc_of_match[] = {
                .compatible = "amlogic, meson-mmc-sm1",
                .data = &mmc_data_sm1,
        },
+       {
+               .compatible = "amlogic, meson-mmc-tm2",
+               .data = &mmc_data_tm2,
+       },
 
        {}
 };
index 8182df3..78f731c 100644 (file)
@@ -193,6 +193,7 @@ enum mmc_chip_e {
        MMC_CHIP_TL1 = 0X2b,
        MMC_CHIP_G12B = 0x29b,
        MMC_CHIP_SM1 = 0X2C,
+       MMC_CHIP_TM2 = 0X2D,
 };
 
 struct mmc_phase {