2003-07-08 Michael Snyder <msnyder@redhat.com>

        * allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s,
        fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s,
        float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s,
        fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s,
        shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.

diff --git a/sim/testsuite/sim/sh/float.s b/sim/testsuite/sim/sh/float.s
new file mode 100644 (file)
index 0000000..e5a3bc6
--- /dev/null
+++ b/sim/testsuite/sim/sh/float.s
@@ -0,0 +1,149 @@
+# sh testcase for float 
+# mach: sh
+# as(sh):      -defsym sim_cpu=0
+
+       .include "testutils.inc"
+
+       start
+
+float_pos:
+       set_grs_a5a5
+       set_fprs_a5a5
+       single_prec
+       mov     #3, r0
+       lds     r0, fpul
+       float   fpul, fr2
+
+       # Check the result.
+       fldi1   fr0
+       fldi1   fr1
+       fadd    fr0, fr1
+       fadd    fr0, fr1
+       fcmp/eq fr1, fr2
+       bt      float_neg
+       fail
+
+float_neg:     
+       mov     #3, r0
+       neg     r0, r0
+       lds     r0, fpul
+       float   fpul, fr2
+
+       # Check the result.
+       fldi1   fr0
+       fldi1   fr1
+       fadd    fr0, fr1
+       fadd    fr0, fr1
+       fneg    fr1
+       fcmp/eq fr1, fr2
+       bt      .L0
+       fail
+.L0:
+       assertreg0      -3
+       test_gr_a5a5    r1
+       test_gr_a5a5    r2
+       test_gr_a5a5    r3
+       test_gr_a5a5    r4
+       test_gr_a5a5    r5
+       test_gr_a5a5    r6
+       test_gr_a5a5    r7
+       test_gr_a5a5    r8
+       test_gr_a5a5    r9
+       test_gr_a5a5    r10
+       test_gr_a5a5    r11
+       test_gr_a5a5    r12
+       test_gr_a5a5    r13
+       test_gr_a5a5    r14
+
+       assert_fpreg_i   1, fr0
+       assert_fpreg_i  -3, fr1
+       assert_fpreg_i  -3, fr2 
+       test_fpr_a5a5   fr3
+       test_fpr_a5a5   fr4
+       test_fpr_a5a5   fr5
+       test_fpr_a5a5   fr6
+       test_fpr_a5a5   fr7
+       test_fpr_a5a5   fr8
+       test_fpr_a5a5   fr9
+       test_fpr_a5a5   fr10
+       test_fpr_a5a5   fr11
+       test_fpr_a5a5   fr12
+       test_fpr_a5a5   fr13
+       test_fpr_a5a5   fr14
+       test_fpr_a5a5   fr15
+
+double_pos:
+       set_grs_a5a5
+       set_fprs_a5a5
+       double_prec
+       mov     #3, r0
+       lds     r0, fpul
+       float   fpul, dr4
+
+       # check the result.
+       fldi1   fr0
+       fldi1   fr1
+       single_prec
+       fadd    fr0, fr1
+       fadd    fr0, fr1
+       double_prec
+       _s2d    fr1, dr2
+       fcmp/eq dr2, dr4
+       bt      double_neg
+       fail
+
+double_neg:
+       double_prec
+       mov     #3, r0
+       neg     r0, r0
+       lds     r0, fpul
+       float   fpul, dr4
+
+       # check the result.
+       fldi1   fr0
+       fldi1   fr1
+       single_prec
+       fadd    fr0, fr1
+       fadd    fr0, fr1
+       fneg    fr1
+       double_prec
+       _s2d    fr1, dr2
+       fcmp/eq dr2, dr4
+       bt      .L2
+       fail
+.L2:
+       assertreg0      -3
+       test_gr_a5a5    r1
+       test_gr_a5a5    r2
+       test_gr_a5a5    r3
+       test_gr_a5a5    r4
+       test_gr_a5a5    r5
+       test_gr_a5a5    r6
+       test_gr_a5a5    r7
+       test_gr_a5a5    r8
+       test_gr_a5a5    r9
+       test_gr_a5a5    r10
+       test_gr_a5a5    r11
+       test_gr_a5a5    r12
+       test_gr_a5a5    r13
+       test_gr_a5a5    r14
+
+       single_prec
+       assert_fpreg_i   1, fr0
+       assert_fpreg_i  -3, fr1
+       double_prec
+       assert_dpreg_i  -3, dr2
+       assert_dpreg_i  -3, dr4
+       test_fpr_a5a5   fr6
+       test_fpr_a5a5   fr7
+       test_fpr_a5a5   fr8
+       test_fpr_a5a5   fr9
+       test_fpr_a5a5   fr10
+       test_fpr_a5a5   fr11
+       test_fpr_a5a5   fr12
+       test_fpr_a5a5   fr13
+       test_fpr_a5a5   fr14
+       test_fpr_a5a5   fr15
+
+       pass
+       exit 0

diff --git a/sim/testsuite/sim/sh/fmac.s b/sim/testsuite/sim/sh/fmac.s
new file mode 100644 (file)
index 0000000..eba1da5
--- /dev/null
+++ b/sim/testsuite/sim/sh/fmac.s
@@ -0,0 +1,98 @@
+# sh testcase for fmac 
+# mach: sh
+# as(sh):      -defsym sim_cpu=0
+
+       .include "testutils.inc"
+
+       start
+fmac_:
+       set_grs_a5a5
+       set_fprs_a5a5
+       # 0.0 * x + y = y.
+
+       fldi0   fr0
+       fldi1   fr1
+       fldi1   fr2
+       fmac    fr0, fr1, fr2
+       # check result.
+       fldi1   fr0
+       fcmp/eq fr0, fr2
+       bt      .L0
+       fail
+.L0:
+       # x * y + 0.0 = x * y.
+
+       fldi1   fr0
+       fldi1   fr1
+       fldi0   fr2
+       # double it.
+       fadd    fr1, fr2
+       fmac    fr0, fr1, fr2
+       # check result.
+       fldi1   fr0
+       fadd    fr0, fr0
+       fcmp/eq fr0, fr2
+       bt      .L1
+       fail
+.L1:   
+       # x * 0.0 + y = y.
+
+       fldi1   fr0
+       fldi0   fr1
+       fldi1   fr2
+       fadd    fr2, fr2
+       fmac    fr0, fr1, fr2
+       # check result.
+       fldi1   fr0
+       # double fr0.
+       fadd    fr0, fr0
+       fcmp/eq fr0, fr2
+       bt      .L2
+       fail
+.L2:
+       # x * 0.0 + 0.0 = 0.0
+
+       fldi1   fr0
+       fadd    fr0, fr0
+       fldi0   fr1
+       fldi0   fr2
+       fmac    fr0, fr1, fr2
+       # check result.
+       fldi0   fr0
+       fcmp/eq fr0, fr2
+       bt      .L3
+       fail
+.L3:   
+       # 0.0 * x + 0.0 = 0.0.
+
+       fldi0   fr0
+       fldi1   fr1
+       # double it.
+       fadd    fr1, fr1
+       fldi0   fr2
+       fmac    fr0, fr1, fr2
+       # check result.
+       fldi0   fr0
+       fcmp/eq fr0, fr2
+       bt      .L4
+       fail
+.L4:
+       test_grs_a5a5
+       assert_fpreg_i  0, fr0
+       assert_fpreg_i  2, fr1
+       assert_fpreg_i  0, fr2
+       test_fpr_a5a5   fr3
+       test_fpr_a5a5   fr4
+       test_fpr_a5a5   fr5
+       test_fpr_a5a5   fr6
+       test_fpr_a5a5   fr7
+       test_fpr_a5a5   fr8
+       test_fpr_a5a5   fr9
+       test_fpr_a5a5   fr10
+       test_fpr_a5a5   fr11
+       test_fpr_a5a5   fr12
+       test_fpr_a5a5   fr13
+       test_fpr_a5a5   fr14
+       test_fpr_a5a5   fr15
+       pass
+       exit 0

diff --git a/sim/testsuite/sim/sh/fmov.s b/sim/testsuite/sim/sh/fmov.s
new file mode 100644 (file)
index 0000000..29c51b5
--- /dev/null
+++ b/sim/testsuite/sim/sh/fmov.s
@@ -0,0 +1,322 @@
+# sh testcase for all fmov instructions
+# mach: sh
+# as(sh):      -defsym sim_cpu=0
+
+       .include "testutils.inc"
+
+       .macro init
+       fldi0   fr0
+       fldi1   fr1
+       fldi1   fr2
+       fldi1   fr3
+       .endm
+
+       start
+
+fmov1: # Test fr -> fr.
+       set_grs_a5a5
+       set_fprs_a5a5
+       init
+       single_prec
+       sz_32
+       fmov    fr0, fr1
+       # Ensure fr0 and fr1 are now equal.
+       fcmp/eq fr0, fr1
+       bt      fmov2
+       fail
+
+fmov2: # Test dr -> dr.
+       init
+       double_prec
+       sz_64
+       fmov    dr0, dr2
+       # Ensure dr0 and dr2 are now equal.
+       fcmp/eq dr0, dr2
+       bt      fmov3
+       fail
+
+fmov3: # Test dr -> xd and xd -> dr.
+       init
+       sz_64
+       fmov    dr0, xd0
+       # Ensure dr0 and xd0 are now equal.
+       fmov    xd0, dr2
+       fcmp/eq dr0, dr2
+       bt      fmov4
+       fail
+
+fmov4: # Test xd -> xd.
+       init
+       sz_64
+       double_prec
+       fmov    dr0, xd0
+       fmov    xd0, xd2
+       fmov    xd2, dr2
+       # Ensure dr0 and dr2 are now equal.
+       fcmp/eq dr0, dr2
+       bt      .L0
+       fail
+
+       # FIXME: test fmov.s fr -> @gr,      fmov dr -> @gr
+       # FIXME: test fmov.s @gr -> fr,      fmov @gr -> dr
+       # FIXME: test fmov.s @gr+ -> fr,     fmov @gr+ -> dr
+       # FIXME: test fmov.s fr -> @-gr,     fmov dr -> @-gr
+       # FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr
+       # FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr)
+       
+.L0:
+       test_grs_a5a5
+       sz_32
+       single_prec
+       assert_fpreg_i  0, fr0
+       assert_fpreg_i  1, fr1
+       assert_fpreg_i  0, fr2
+       assert_fpreg_i  1, fr3
+       test_fpr_a5a5   fr4
+       test_fpr_a5a5   fr5
+       test_fpr_a5a5   fr6
+       test_fpr_a5a5   fr7
+       test_fpr_a5a5   fr8
+       test_fpr_a5a5   fr9
+       test_fpr_a5a5   fr10
+       test_fpr_a5a5   fr11
+       test_fpr_a5a5   fr12
+       test_fpr_a5a5   fr13
+       test_fpr_a5a5   fr14
+       test_fpr_a5a5   fr15
+
+fmov5: # Test fr -> @rn and @rn -> fr.
+       init
+       sz_32
+       single_prec
+       # FIXME!  Use a reserved memory location!
+       mov     #40, r0
+       shll8   r0
+       fmov    fr0, @r0
+       fmov    @r0, fr1
+       fcmp/eq fr0, fr1
+       bt      fmov6
+       fail
+
+fmov6: # Test dr -> @rn and @rn -> dr.
+       init
+       sz_64
+       double_prec
+       mov     #40, r0
+       shll8   r0
+       fmov    dr0, @r0
+       fmov    @r0, dr2
+       fcmp/eq dr0, dr2
+       bt      fmov7
+       fail
+
+fmov7: # Test xd -> @rn and @rn -> xd.
+       init
+       sz_64
+       double_prec
+       mov     #40, r0
+       shll8   r0
+       fmov    dr0, xd0
+       fmov    xd0, @r0
+       fmov    @r0, xd2
+       fmov    xd2, dr2
+       fcmp/eq dr0, dr2
+       bt      fmov8
+       fail
+
+fmov8: # Test fr -> @-rn.
+       init
+       sz_32
+       single_prec
+       mov     #40, r0
+       shll8   r0
+       # Preserve.
+       mov     r0, r1
+       fmov    fr0, @-r0
+       fmov    @r0, fr2
+       fcmp/eq fr0, fr2
+       bt      f8b
+       fail
+f8b:   # check pre-dec.
+       add     #4, r0
+       cmp/eq  r0, r1
+       bt      fmov9
+       fail
+
+fmov9: # Test dr -> @-rn.
+       init
+       sz_64
+       double_prec
+       mov     #40, r0
+       shll8   r0
+       # Preserve r0.
+       mov     r0, r1
+       fmov    dr0, @-r0
+       fmov    @r0, dr2
+       fcmp/eq dr0, dr2
+       bt      f9b
+       fail
+f9b:   # check pre-dec.
+       add     #8, r0
+       cmp/eq  r0, r1
+       bt      fmov10
+       fail
+
+fmov10:        # Test xd -> @-rn.
+       init
+       sz_64
+       double_prec
+       mov     #40, r0
+       shll8   r0
+       # Preserve r0.
+       mov     r0, r1
+       fmov    dr0, xd0
+       fmov    xd0, @-r0
+       fmov    @r0, xd2
+       fmov    xd2, dr2
+       fcmp/eq dr0, dr2
+       bt      f10b
+       fail
+f10b:  # check pre-dec.
+       add     #8, r0
+       cmp/eq  r0, r1
+       bt      fmov11
+       fail
+
+fmov11:        # Test @rn+ -> fr.
+       init
+       sz_32
+       single_prec
+       mov     #40, r0
+       shll8   r0
+       # Preserve r0.
+       mov     r0, r1
+       fmov    fr0, @r0
+       fmov    @r0+, fr2
+       fcmp/eq fr0, fr2
+       bt      f11b
+       fail
+f11b:  # check post-inc.
+       add     #4, r1
+       cmp/eq  r0, r1
+       bt      fmov12
+       fail
+
+fmov12:        # Test @rn+ -> dr.
+       init
+       sz_64
+       double_prec
+       mov     #40, r0
+       shll8   r0
+       # preserve r0.
+       mov     r0, r1
+       fmov    dr0, @r0
+       fmov    @r0+, dr2
+       fcmp/eq dr0, dr2
+       bt      f12b
+       fail
+f12b:  # check post-inc.
+       add     #8, r1
+       cmp/eq  r0, r1
+       bt      fmov13
+       fail
+
+fmov13:        # Test @rn -> xd.
+       init
+       sz_64
+       double_prec
+       mov     #40, r0
+       shll8   r0
+       # Preserve r0.
+       mov     r0, r1
+       fmov    dr0, xd0
+       fmov    xd0, @r0
+       fmov    @r0+, xd2
+       fmov    xd2, dr2
+       fcmp/eq dr0, dr2
+       bt      f13b
+       fail
+f13b:
+       add     #8, r1
+       cmp/eq  r0, r1
+       bt      fmov14
+       fail
+
+fmov14:        # Test fr -> @(r0,rn), @(r0, rn) -> fr.
+       init
+       sz_32
+       single_prec
+       mov     #40, r0
+       shll8   r0
+       mov     #0, r1
+       fmov    fr0, @(r0, r1)
+       fmov    @(r0, r1), fr1
+       fcmp/eq fr0, fr1
+       bt      fmov15
+       fail
+
+fmov15:        # Test dr -> @(r0, rn), @(r0, rn) -> dr.
+       init
+       sz_64
+       double_prec
+       mov     #40, r0
+       shll8   r0
+       mov     #0, r1
+       fmov    dr0, @(r0, r1)
+       fmov    @(r0, r1), dr2
+       fcmp/eq dr0, dr2
+       bt      fmov16
+       fail
+
+fmov16:        # Test xd -> @(r0, rn), @(r0, rn) -> xd.
+       init
+       sz_64
+       double_prec
+       mov     #40, r0
+       shll8   r0
+       mov     #0, r1
+       fmov    dr0, xd0
+       fmov    xd0, @(r0, r1)
+       fmov    @(r0, r1), xd2
+       fmov    xd2, dr2
+       fcmp/eq dr0, dr2
+       bt      .L1
+       fail
+.L1:
+       assertreg0      0x2800
+       assertreg       0, r1
+       test_gr_a5a5    r2
+       test_gr_a5a5    r3
+       test_gr_a5a5    r4
+       test_gr_a5a5    r5
+       test_gr_a5a5    r6
+       test_gr_a5a5    r7
+       test_gr_a5a5    r8
+       test_gr_a5a5    r9
+       test_gr_a5a5    r10
+       test_gr_a5a5    r11
+       test_gr_a5a5    r12
+       test_gr_a5a5    r13
+       test_gr_a5a5    r14
+
+       sz_32
+       single_prec
+       assert_fpreg_i  0, fr0
+       assert_fpreg_i  1, fr1
+       assert_fpreg_i  0, fr2
+       assert_fpreg_i  1, fr3
+       test_fpr_a5a5   fr4
+       test_fpr_a5a5   fr5
+       test_fpr_a5a5   fr6
+       test_fpr_a5a5   fr7
+       test_fpr_a5a5   fr8
+       test_fpr_a5a5   fr9
+       test_fpr_a5a5   fr10
+       test_fpr_a5a5   fr11
+       test_fpr_a5a5   fr12
+       test_fpr_a5a5   fr13
+       test_fpr_a5a5   fr14
+       test_fpr_a5a5   fr15
+
+       pass
+       exit 0

diff --git a/sim/testsuite/sim/sh/fmul.s b/sim/testsuite/sim/sh/fmul.s
new file mode 100644 (file)
index 0000000..81a2545
--- /dev/null
+++ b/sim/testsuite/sim/sh/fmul.s
@@ -0,0 +1,116 @@
+# sh testcase for fmul 
+# mach: sh
+# as(sh):      -defsym sim_cpu=0
+
+       .include "testutils.inc"
+
+       .macro init
+       fldi0 fr0
+       fldi1 fr1
+       fldi1 fr2
+       fadd fr2, fr2
+       .endm
+
+       start
+fmul_single:
+       set_grs_a5a5
+       set_fprs_a5a5
+       # 0.0 * 0.0 = 0.0.
+       init
+       fmul    fr0, fr0
+       assert_fpreg_i  0, fr0
+
+       # 0.0 * 1.0 = 0.0.
+       init
+       fmul    fr1, fr0
+       assert_fpreg_i  0, fr0
+
+       # 1.0 * 0.0 = 0.0.
+       init
+       fmul    fr0, fr1
+       assert_fpreg_i  0, fr1
+
+       # 1.0 * 1.0 = 1.0.
+       init
+       fmul    fr1, fr1
+       assert_fpreg_i  1, fr1
+
+       # 2.0 * 1.0 = 2.0.
+       init
+       fmul    fr2, fr1
+       assert_fpreg_i  2, fr1
+
+       test_grs_a5a5
+       assert_fpreg_i  0, fr0
+       assert_fpreg_i  2, fr1
+       assert_fpreg_i  2, fr2
+       test_fpr_a5a5   fr3
+       test_fpr_a5a5   fr4
+       test_fpr_a5a5   fr5
+       test_fpr_a5a5   fr6
+       test_fpr_a5a5   fr7
+       test_fpr_a5a5   fr8
+       test_fpr_a5a5   fr9
+       test_fpr_a5a5   fr10
+       test_fpr_a5a5   fr11
+       test_fpr_a5a5   fr12
+       test_fpr_a5a5   fr13
+       test_fpr_a5a5   fr14
+       test_fpr_a5a5   fr15
+
+       .macro dinit
+       fldi0 fr0
+       fldi1 fr2
+       fldi1 fr4
+       single_prec
+       fadd fr4, fr4
+       double_prec
+       _s2d fr0, dr0
+       _s2d fr2, dr2
+       _s2d fr4, dr4
+       .endm
+       
+fmul_double:
+       double_prec
+       # 0.0 * 0.0 = 0.0.
+       dinit
+       fmul    dr0, dr0
+       assert_dpreg_i  0, dr0
+
+       # 0.0 * 1.0 = 0.0.
+       dinit
+       fmul    dr2, dr0
+       assert_dpreg_i  0, dr0
+
+       # 1.0 * 0.0 = 0.0.
+       dinit
+       fmul    dr0, dr2
+       assert_dpreg_i  0, dr2
+
+       # 1.0 * 1.0 = 1.0.
+       dinit
+       fmul    dr2, dr2
+       assert_dpreg_i  1, dr2
+
+       # 2.0 * 1.0 = 2.0.
+       dinit
+       fmul    dr4, dr2
+       assert_dpreg_i  2, dr2
+
+       test_grs_a5a5
+       assert_dpreg_i  0, dr0
+       assert_dpreg_i  2, dr2
+       assert_dpreg_i  2, dr4
+       test_fpr_a5a5   fr6
+       test_fpr_a5a5   fr7
+       test_fpr_a5a5   fr8
+       test_fpr_a5a5   fr9
+       test_fpr_a5a5   fr10
+       test_fpr_a5a5   fr11
+       test_fpr_a5a5   fr12
+       test_fpr_a5a5   fr13
+       test_fpr_a5a5   fr14
+       test_fpr_a5a5   fr15
+
+       pass
+       exit 0

diff --git a/sim/testsuite/sim/sh/fneg.s b/sim/testsuite/sim/sh/fneg.s
new file mode 100644 (file)
index 0000000..dd5fe5d
--- /dev/null
+++ b/sim/testsuite/sim/sh/fneg.s
@@ -0,0 +1,112 @@
+# sh testcase for fneg 
+# mach: sh
+# as(sh):      -defsym sim_cpu=0
+
+       .include "testutils.inc"
+
+       start
+fneg_single:
+       set_grs_a5a5
+       set_fprs_a5a5
+       # neg(0.0) = 0.0.
+       fldi0   fr0
+       fldi0   fr1
+       fneg    fr0
+       fcmp/eq fr0, fr1
+       bt      .L0
+       fail
+.L0:
+       # neg(1.0) = fsub(0,1)
+       fldi1   fr0
+       fneg    fr0
+       fldi0   fr1
+       fldi1   fr2
+       fsub    fr2, fr1
+       fcmp/eq fr0, fr1
+       bt      .L1
+       fail
+.L1:
+       # neg(neg(1.0)) = 1.0.
+       fldi1   fr0
+       fldi1   fr1
+       fneg    fr0
+       fneg    fr0
+       fcmp/eq fr0, fr1
+       bt      .L2
+       fail
+.L2:
+       test_grs_a5a5
+       assert_fpreg_i  1, fr0
+       assert_fpreg_i  1, fr1
+       assert_fpreg_i  1, fr2
+       test_fpr_a5a5   fr3
+       test_fpr_a5a5   fr4
+       test_fpr_a5a5   fr5
+       test_fpr_a5a5   fr6
+       test_fpr_a5a5   fr7
+       test_fpr_a5a5   fr8
+       test_fpr_a5a5   fr9
+       test_fpr_a5a5   fr10
+       test_fpr_a5a5   fr11
+       test_fpr_a5a5   fr12
+       test_fpr_a5a5   fr13
+       test_fpr_a5a5   fr14
+       test_fpr_a5a5   fr15
+
+fneg_double:
+       set_grs_a5a5
+       set_fprs_a5a5
+       double_prec
+       # neg(0.0) = 0.0.
+       fldi0   fr0
+       fldi0   fr2
+       _s2d    fr0, dr0
+       _s2d    fr2, dr2
+       fneg    dr0
+       fcmp/eq dr0, dr2
+       bt      .L10
+       fail
+.L10:
+       # neg(1.0) = fsub(0,1)
+       fldi1   fr0
+       _s2d    fr0, dr0
+       fneg    dr0
+       fldi0   fr2
+       fldi1   fr3
+       single_prec
+       fsub    fr3, fr2
+       double_prec
+       _s2d    fr2, dr2
+       fcmp/eq dr0, dr2
+       bt      .L11
+       fail
+.L11:
+       # neg(neg(1.0)) = 1.0.
+       fldi1   fr0
+       _s2d    fr0, dr0
+       fldi1   fr2
+       _s2d    fr2, dr2
+       fneg    dr2
+       fneg    dr2
+       fcmp/eq dr0, dr2
+       bt      .L12
+       fail
+.L12:
+       test_grs_a5a5
+       assert_dpreg_i  1, dr0
+       assert_dpreg_i  1, dr2
+       test_fpr_a5a5   fr4
+       test_fpr_a5a5   fr5
+       test_fpr_a5a5   fr6
+       test_fpr_a5a5   fr7
+       test_fpr_a5a5   fr8
+       test_fpr_a5a5   fr9
+       test_fpr_a5a5   fr10
+       test_fpr_a5a5   fr11
+       test_fpr_a5a5   fr12
+       test_fpr_a5a5   fr13
+       test_fpr_a5a5   fr14
+       test_fpr_a5a5   fr15
+
+       pass
+       exit 0

diff --git a/sim/testsuite/sim/sh/frchg.s b/sim/testsuite/sim/sh/frchg.s
new file mode 100644 (file)
index 0000000..c5dc099
--- /dev/null
+++ b/sim/testsuite/sim/sh/frchg.s
@@ -0,0 +1,30 @@
+# sh testcase for frchg
+# mach: sh
+# as(sh):      -defsym sim_cpu=0
+
+       .include "testutils.inc"
+
+       start
+       set_grs_a5a5
+       set_fprs_a5a5
+       sts     fpscr, r0
+       assertreg0      0
+       frchg
+       sts     fpscr, r0
+       assertreg0      0x200000
+       frchg
+       sts     fpscr, r0
+       assertreg0      0
+       frchg
+       sts     fpscr, r0
+       assertreg0      0x200000
+       frchg
+       sts     fpscr, r0
+       assertreg0      0
+
+       set_greg        0xa5a5a5a5, r0
+       test_grs_a5a5
+       test_fprs_a5a5
+
+       pass
+       exit 0

diff --git a/sim/testsuite/sim/sh/fschg.s b/sim/testsuite/sim/sh/fschg.s
new file mode 100644 (file)
index 0000000..7454787
--- /dev/null
+++ b/sim/testsuite/sim/sh/fschg.s
@@ -0,0 +1,29 @@
+# sh testcase for fschg
+# mach: sh
+# as(sh):      -defsym sim_cpu=0
+
+       .include "testutils.inc"
+
+       start
+       set_grs_a5a5
+       set_fprs_a5a5
+       sts     fpscr, r0
+       assertreg0      0
+       fschg
+       sts     fpscr, r0
+       assertreg0      0x100000
+       fschg
+       sts     fpscr, r0
+       assertreg0      0
+       fschg
+       sts     fpscr, r0
+       assertreg0      0x100000
+       fschg
+       sts     fpscr, r0
+       assertreg0      0
+
+       set_greg 0xa5a5a5a5 r0
+       test_grs_a5a5
+       test_fprs_a5a5
+       pass
+       exit 0