2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* archures.c (bfd_architecture): New machine
+ bfd_mach_mips_gs264e.
+ * bfd-in2.h (bfd_architecture): Likewise.
+ * cpu-mips.c (enum I_xxx): Likewise.
+ (arch_info_struct): Likewise.
+ * elfxx-mips.c (_bfd_elf_mips_mach): Handle
+ E_MIPS_MACH_GS264E.
+ (mips_set_isa_flags): Likewise.
+ (mips_mach_extensions): Map bfd_mach_mips_gs264e to
+ bfd_mach_mips_gs464e extension.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * archures.c (bfd_architecture): New machine
bfd_mach_mips_gs464e.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (enum I_xxx): Likewise.
.#define bfd_mach_mips_loongson_2f 3002
.#define bfd_mach_mips_gs464 3003
.#define bfd_mach_mips_gs464e 3004
+.#define bfd_mach_mips_gs264e 3005
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01. *}
.#define bfd_mach_mips_octeon 6501
.#define bfd_mach_mips_octeonp 6601
#define bfd_mach_mips_loongson_2f 3002
#define bfd_mach_mips_gs464 3003
#define bfd_mach_mips_gs464e 3004
+#define bfd_mach_mips_gs264e 3005
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01. */
#define bfd_mach_mips_octeon 6501
#define bfd_mach_mips_octeonp 6601
I_loongson_2f,
I_gs464,
I_gs464e,
+ I_gs264e,
I_mipsocteon,
I_mipsocteonp,
I_mipsocteon2,
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
N (64, 64, bfd_mach_mips_gs464, "mips:gs464", FALSE, NN(I_gs464)),
N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e", FALSE, NN(I_gs464e)),
+ N (64, 64, bfd_mach_mips_gs264e, "mips:gs264e", FALSE, NN(I_gs264e)),
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
case E_MIPS_MACH_GS464E:
return bfd_mach_mips_gs464e;
+ case E_MIPS_MACH_GS264E:
+ return bfd_mach_mips_gs264e;
+
case E_MIPS_MACH_OCTEON3:
return bfd_mach_mips_octeon3;
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464E;
break;
+ case bfd_mach_mips_gs264e:
+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS264E;
+ break;
+
case bfd_mach_mips_octeon:
case bfd_mach_mips_octeonp:
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
{ bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
{ bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+ { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
{ bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
{ bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+ * NEWS: Mention Loongson 2K1000 proccessor support.
+ * readelf.c (get_machine_flags): Handle gs264e.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
* readelf.c (get_machine_flags): Handle gs464e.
-*- text -*-
+* The MIPS port now supports the Loongson 2K1000 processor which implements
+ the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE, Loongson-ext ASE,
+ Loongson-ext2 ASE and MSA ASE instructions. Add -march=gs264e option for
+ Loongson 2K1000 processor.
+
* The MIPS port now supports the Loongson 3A2000/3A3000 processor which
implements the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE,
Loongson-ext ASE and Loongson-ext2 ASE instructions. Add -march=gs464e
case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
case E_MIPS_MACH_GS464: strcat (buf, ", gs464"); break;
case E_MIPS_MACH_GS464E: strcat (buf, ", gs464e"); break;
+ case E_MIPS_MACH_GS264E: strcat (buf, ", gs264e"); break;
case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
E_MIPS_MACH_LS2F = 0x00A10000,
E_MIPS_MACH_GS464 = 0x00A20000,
E_MIPS_MACH_GS464E = 0x00A30000,
+ E_MIPS_MACH_GS264E = 0x00A40000,
};
// MIPS architecture
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
+ (mips_cpu_info_table): Add gs264e descriptors.
+ * doc/as.texi (march table): Add gs264e.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
(mips_cpu_info_table): Add gs464e descriptors.
* doc/as.texi (march table): Add gs464e.
|| (ISA) == ISA_MIPS64R6 \
|| (CPU) == CPU_R5900) \
&& ((CPU) != CPU_GS464 \
- || (CPU) != CPU_GS464E))
+ || (CPU) != CPU_GS464E \
+ || (CPU) != CPU_GS264E))
/* Return true if ISA supports move to/from high part of a 64-bit
floating-point register. */
ISA_MIPS64R2, CPU_GS464 },
{ "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E },
+ { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+ | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E },
/* Cavium Networks Octeon CPU core */
{ "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
loongson2f,
gs464,
gs464e,
+gs264e,
octeon,
octeon+,
octeon2,
mach_mips_loongson_2f = 3002,
mach_mips_gs464 = 3003,
mach_mips_gs464e = 3004,
+ mach_mips_gs264e = 3005,
mach_mips_sb1 = 12310201, // octal 'SB', 01
mach_mips_octeon = 6501,
mach_mips_octeonp = 6601,
this->add_extension(mach_mips_octeon2, mach_mips_octeonp);
this->add_extension(mach_mips_octeonp, mach_mips_octeon);
this->add_extension(mach_mips_octeon, mach_mipsisa64r2);
+ this->add_extension(mach_mips_gs264e, mach_mips_gs464e);
this->add_extension(mach_mips_gs464e, mach_mips_gs464);
this->add_extension(mach_mips_gs464, mach_mipsisa64r2);
case elfcpp::E_MIPS_MACH_GS464E:
return mach_mips_gs464e;
+ case elfcpp::E_MIPS_MACH_GS264E:
+ return mach_mips_gs264e;
+
case elfcpp::E_MIPS_MACH_OCTEON3:
return mach_mips_octeon3;
return "mips:gs464";
case elfcpp::E_MIPS_MACH_GS464E:
return "mips:gs464e";
+ case elfcpp::E_MIPS_MACH_GS264E:
+ return "mips:gs264e";
case elfcpp::E_MIPS_MACH_OCTEON:
return "mips:octeon";
case elfcpp::E_MIPS_MACH_OCTEON2:
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
+ * opcode/mips.h (CPU_XXX): New CPU_GS264E.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
* opcode/mips.h (CPU_XXX): New CPU_GS464E.
#define E_MIPS_MACH_LS2F 0x00A10000
#define E_MIPS_MACH_GS464 0x00A20000
#define E_MIPS_MACH_GS464E 0x00A30000
+#define E_MIPS_MACH_GS264E 0x00A40000
\f
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
#define CPU_LOONGSON_2F 3002
#define CPU_GS464 3003
#define CPU_GS464E 3004
+#define CPU_GS264E 3005
#define CPU_OCTEON 6501
#define CPU_OCTEONP 6601
#define CPU_OCTEON2 6502
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
+ gs264e and gs464e.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
gs464e and gs464.
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
{ gs464e o32 } \
MIPS64r2 "None" \
{ "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
+good_combination { "-march=gs264e -32" "-march=gs464e -32" } \
+ { gs264e o32 } \
+ MIPS64r2 "None" \
+ { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+ * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
+
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
| ASE_LOONGSON_EXT2, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
mips_hwr_names_numeric },
+ { "g264e", 1, bfd_mach_mips_gs464e, CPU_GS264E,
+ ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+ | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, mips_cp0_names_numeric, NULL,
+ 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
+
{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
mips_cp1_names_mips3264, mips_hwr_names_numeric },