board: toradex: move RGMII delays to PHY side

The RGMII link delays can be set on either MAC or PHY side. Set the
rgmii-id PHY mode for FEC and remove FEC_ENET_ENABLE_.XC_DELAY
setting, so that these definitions aren't used anymore throughout
the U-Boot.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts
index 5187b79..0d8d3b3 100644 (file)
--- a/arch/arm/dts/fsl-imx8qm-apalis.dts
+++ b/arch/arm/dts/fsl-imx8qm-apalis.dts
@@ -503,7 +503,7 @@
        pinctrl-0 = <&pinctrl_fec1>;
        fsl,magic-packet;
        phy-handle = <&ethphy0>;
-       phy-mode = "rgmii";
+       phy-mode = "rgmii-id";
        phy-reset-duration = <10>;
        phy-reset-gpios = <&gpio1 11 1>;
        status = "okay";

diff --git a/arch/arm/dts/fsl-imx8qxp-apalis.dts b/arch/arm/dts/fsl-imx8qxp-apalis.dts
index 6bd231b..9cb3d3a 100644 (file)
--- a/arch/arm/dts/fsl-imx8qxp-apalis.dts
+++ b/arch/arm/dts/fsl-imx8qxp-apalis.dts
@@ -229,7 +229,7 @@
        pinctrl-0 = <&pinctrl_fec1>;
        fsl,magic-packet;
        phy-handle = <&ethphy0>;
-       phy-mode = "rgmii";
+       phy-mode = "rgmii-id";
        phy-reset-duration = <10>;
        phy-reset-post-delay = <150>;
        phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;

diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index 0260eb4..8fe3226 100644 (file)
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -21,8 +21,6 @@
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
 /* Networking */
-#define FEC_ENET_ENABLE_TXC_DELAY
-
 #define CONFIG_TFTP_TSIZE
 
 #define CONFIG_IPADDR                  192.168.10.2

diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h
index a84b8e6..fdb0da3 100644 (file)
--- a/include/configs/apalis-imx8x.h
+++ b/include/configs/apalis-imx8x.h
@@ -25,9 +25,6 @@
 #define CONFIG_NETMASK                 255.255.255.0
 #define CONFIG_SERVERIP                        192.168.10.1
 
-#define FEC_ENET_ENABLE_TXC_DELAY
-#define FEC_ENET_ENABLE_RXC_DELAY
-
 #define MEM_LAYOUT_ENV_SETTINGS \
        "kernel_addr_r=0x80280000\0" \
        "fdt_addr_r=0x83100000\0" \