(enum amd64_regnum): New.
(X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, X86_64_RDI_REGNUM)
(X86_64_RBP_REGNUM, X86_64_RSP_REGNUM, X86_64_RIP_REGNUM)
(X86_64_EFLAGS_REGNUM, X86_64_ST0_REGNUM, X86_64_XMM0_REGNUM)
(X86_64_XMM1_REGNUM): Removed.
(AMD64_NUM_GREGS): Renamed from X86_64_NUM_GREGS.
(amd64_init_abi, amd64_supply_fxsave, amd64_fill_fxsave): Adjust
prototypes for renamed functions.
* x86-64-tdep.c: Fix typo.
(amd64_dwarf_regmap): Use constants from `enum amd64_regnum' for
register numbers.
(amd64_return_value, amd64_push_arguments, amd64_push_dummy_call):
Use constants from `enum amd64_regnum' for register numbers.
(AMD64_NUM_SAVED_REGS): Adjust for renamed macros.
(amd64_analyze_prologue, amd64_frame_cache,
amd64_sigtramp_frame_cache): Use constants from `enum
amd64_regnum' for register numbers.
(amd64_supply_fpregset): Adjust for renamed functions.
(amd64_init_abi): Rename from x86_64_init_abi. Use constants from
`enum amd64_regnum' for register numbers.
(I387_ST0_REGNUM): Use constant from `enum amd64_regnum'.
(amd64_supply_fxsave): Rename from x86_64_supply_fxsave.
(amd64_fill_fxsave): Rename fro x86_64_fill_fxsave.
* x86-64-linux-tdep.c (amd64_linux_supply_gregset)
(amd64_linux_fill_gregset): Adjust for renamed macros.
(fetch_core_registers): Adjust for renamed functions.
(amd64_linux_init_abi): Adjust for renamed functions.
* x86-64-linux-nat.c (supply_gregset, fill_gregset): Adjust for
renamed functions.
* amd64-nat.c: Adjust for renamed macros.
* amd64bsd-nat.c (fetch_inferior_registers)
(store_inferior_registers): Use constants from `enum amd64_regnum'
for register numbers. Adjust for renamed variables.
* amd64fbsd-nat.c (supply_gregset, fill_gregset): Adjust for
renamed variables.
(_initialize_amd64fbsd_nat): Use constants from `enum
amd64_regnum' for register numbers.
* amd64fbsd-tdep.c (amd64fbsd_sigcontext_addr): Use constants from
`enum amd64_regnum' for register numbers.
(amd64fbsd_init_abi): Adjust for renamed functions.
* amd64nbsd-tdep.c (amd64nbsd_sigcontext_addr): Use constants from
`enum amd64_regnum' for register numbers.
(amd64nbsd_init_abi): Adjust for renamed functions.
(_initialize_amd64nbsd_ndep): Adjust for renamed macros.
* amd64obsd-tdep.c (amd64obsd_sigcontext_addr): Use constants from
`enum amd64_regnum' for register numbers.
(amd64obsd_init_abi): Adjust for renamed functions.
(_initialize_amd64obsd_ndep): Adjust for renamed macros.
+2004-02-23 Mark Kettenis <kettenis@gnu.org>
+
+ * x86-64-tdep.h: Tewak comment.
+ (enum amd64_regnum): New.
+ (X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, X86_64_RDI_REGNUM)
+ (X86_64_RBP_REGNUM, X86_64_RSP_REGNUM, X86_64_RIP_REGNUM)
+ (X86_64_EFLAGS_REGNUM, X86_64_ST0_REGNUM, X86_64_XMM0_REGNUM)
+ (X86_64_XMM1_REGNUM): Removed.
+ (AMD64_NUM_GREGS): Renamed from X86_64_NUM_GREGS.
+ (amd64_init_abi, amd64_supply_fxsave, amd64_fill_fxsave): Adjust
+ prototypes for renamed functions.
+ * x86-64-tdep.c: Fix typo.
+ (amd64_dwarf_regmap): Use constants from `enum amd64_regnum' for
+ register numbers.
+ (amd64_return_value, amd64_push_arguments, amd64_push_dummy_call):
+ Use constants from `enum amd64_regnum' for register numbers.
+ (AMD64_NUM_SAVED_REGS): Adjust for renamed macros.
+ (amd64_analyze_prologue, amd64_frame_cache,
+ amd64_sigtramp_frame_cache): Use constants from `enum
+ amd64_regnum' for register numbers.
+ (amd64_supply_fpregset): Adjust for renamed functions.
+ (amd64_init_abi): Rename from x86_64_init_abi. Use constants from
+ `enum amd64_regnum' for register numbers.
+ (I387_ST0_REGNUM): Use constant from `enum amd64_regnum'.
+ (amd64_supply_fxsave): Rename from x86_64_supply_fxsave.
+ (amd64_fill_fxsave): Rename fro x86_64_fill_fxsave.
+ * x86-64-linux-tdep.c (amd64_linux_supply_gregset)
+ (amd64_linux_fill_gregset): Adjust for renamed macros.
+ (fetch_core_registers): Adjust for renamed functions.
+ (amd64_linux_init_abi): Adjust for renamed functions.
+ * x86-64-linux-nat.c (supply_gregset, fill_gregset): Adjust for
+ renamed functions.
+ * amd64-nat.c: Adjust for renamed macros.
+ * amd64bsd-nat.c (fetch_inferior_registers)
+ (store_inferior_registers): Use constants from `enum amd64_regnum'
+ for register numbers. Adjust for renamed variables.
+ * amd64fbsd-nat.c (supply_gregset, fill_gregset): Adjust for
+ renamed variables.
+ (_initialize_amd64fbsd_nat): Use constants from `enum
+ amd64_regnum' for register numbers.
+ * amd64fbsd-tdep.c (amd64fbsd_sigcontext_addr): Use constants from
+ `enum amd64_regnum' for register numbers.
+ (amd64fbsd_init_abi): Adjust for renamed functions.
+ * amd64nbsd-tdep.c (amd64nbsd_sigcontext_addr): Use constants from
+ `enum amd64_regnum' for register numbers.
+ (amd64nbsd_init_abi): Adjust for renamed functions.
+ (_initialize_amd64nbsd_ndep): Adjust for renamed macros.
+ * amd64obsd-tdep.c (amd64obsd_sigcontext_addr): Use constants from
+ `enum amd64_regnum' for register numbers.
+ (amd64obsd_init_abi): Adjust for renamed functions.
+ (_initialize_amd64obsd_ndep): Adjust for renamed macros.
+
2004-02-23 Jeff Johnston <jjohnstn@redhat.com>
* breakpoint.c (print_one_breakpoint): Do not output spaces
/* General-purpose register mapping for native 64-bit code. */
int *amd64_native_gregset64_reg_offset;
-int amd64_native_gregset64_num_regs = X86_64_NUM_GREGS;
+int amd64_native_gregset64_num_regs = AMD64_NUM_GREGS;
/* Return the offset of REGNUM within the appropriate native
general-purpose register set. */
return;
}
- if (regnum == -1 || regnum >= X86_64_ST0_REGNUM)
+ if (regnum == -1 || regnum >= AMD64_ST0_REGNUM)
{
struct fpreg fpregs;
(PTRACE_ARG3_TYPE) &fpregs, 0) == -1)
perror_with_name ("Couldn't get floating point status");
- x86_64_supply_fxsave (current_regcache, -1, &fpregs);
+ amd64_supply_fxsave (current_regcache, -1, &fpregs);
}
}
return;
}
- if (regnum == -1 || regnum >= X86_64_ST0_REGNUM)
+ if (regnum == -1 || regnum >= AMD64_ST0_REGNUM)
{
struct fpreg fpregs;
(PTRACE_ARG3_TYPE) &fpregs, 0) == -1)
perror_with_name ("Couldn't get floating point status");
- x86_64_fill_fxsave ((char *) &fpregs, regnum);
+ amd64_fill_fxsave ((char *) &fpregs, regnum);
if (ptrace (PT_SETFPREGS, PIDGET (inferior_ptid),
(PTRACE_ARG3_TYPE) &fpregs, 0) == -1)
void
supply_fpregset (fpregset_t *fpregsetp)
{
- x86_64_supply_fxsave (current_regcache, -1, fpregsetp);
+ amd64_supply_fxsave (current_regcache, -1, fpregsetp);
}
/* Fill register REGNUM (if it is a floating-point register) in
void
fill_fpregset (fpregset_t *fpregsetp, int regnum)
{
- x86_64_fill_fxsave ((char *) fpregsetp, regnum);
+ amd64_fill_fxsave ((char *) fpregsetp, regnum);
}
\f
pointer since these members of `struct sigcontext' are essential
for providing backtraces. */
-#define SC_RIP_OFFSET SC_REG_OFFSET[X86_64_RIP_REGNUM]
-#define SC_RSP_OFFSET SC_REG_OFFSET[X86_64_RSP_REGNUM]
-#define SC_RBP_OFFSET SC_REG_OFFSET[X86_64_RBP_REGNUM]
+#define SC_RIP_OFFSET SC_REG_OFFSET[AMD64_RIP_REGNUM]
+#define SC_RSP_OFFSET SC_REG_OFFSET[AMD64_RSP_REGNUM]
+#define SC_RBP_OFFSET SC_REG_OFFSET[AMD64_RBP_REGNUM]
/* Override the default value for the offset of the program counter
in the sigcontext structure. */
/* The `struct sigcontext' (which really is an `ucontext_t' on
FreeBSD/amd64) lives at a fixed offset in the signal frame. See
<machine/sigframe.h>. */
- sp = frame_unwind_register_unsigned (next_frame, X86_64_RSP_REGNUM);
+ sp = frame_unwind_register_unsigned (next_frame, AMD64_RSP_REGNUM);
return sp + 16;
}
\f
tdep->gregset_num_regs = ARRAY_SIZE (amd64fbsd_r_reg_offset);
tdep->sizeof_gregset = 22 * 8;
- x86_64_init_abi (info, gdbarch);
+ amd64_init_abi (info, gdbarch);
tdep->sigtramp_start = amd64fbsd_sigtramp_start_addr;
tdep->sigtramp_end = amd64fbsd_sigtramp_end_addr;
/* The stack pointer points at `struct sigcontext' upon entry of a
signal trampoline. */
- sp = frame_unwind_register_unsigned (next_frame, X86_64_RSP_REGNUM);
+ sp = frame_unwind_register_unsigned (next_frame, AMD64_RSP_REGNUM);
return sp;
}
\f
tdep->gregset_num_regs = ARRAY_SIZE (amd64nbsd_r_reg_offset);
tdep->sizeof_gregset = 26 * 8;
- x86_64_init_abi (info, gdbarch);
+ amd64_init_abi (info, gdbarch);
tdep->jb_pc_offset = 7 * 8;
_initialize_amd64nbsd_ndep (void)
{
/* The NetBSD/amd64 native dependent code makes this assumption. */
- gdb_assert (ARRAY_SIZE (amd64nbsd_r_reg_offset) == X86_64_NUM_GREGS);
+ gdb_assert (ARRAY_SIZE (amd64nbsd_r_reg_offset) == AMD64_NUM_GREGS);
gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64,
GDB_OSABI_NETBSD_ELF, amd64nbsd_init_abi);
gdb_assert (len >= tdep->sizeof_gregset + I387_SIZEOF_FXSAVE);
i386_supply_gregset (regset, regcache, regnum, regs, tdep->sizeof_gregset);
- x86_64_supply_fxsave (regcache, regnum, (char *)regs + tdep->sizeof_gregset);
+ amd64_supply_fxsave (regcache, regnum, (char *)regs + tdep->sizeof_gregset);
}
static const struct regset *
{
/* The %rsp register points at `struct sigcontext' upon entry of a
signal trampoline. */
- return frame_unwind_register_unsigned (next_frame, X86_64_RSP_REGNUM);
+ return frame_unwind_register_unsigned (next_frame, AMD64_RSP_REGNUM);
}
\f
/* OpenBSD 3.5 or later. */
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- x86_64_init_abi (info, gdbarch);
+ amd64_init_abi (info, gdbarch);
/* Initialize general-purpose register set details. */
tdep->gregset_reg_offset = amd64obsd_r_reg_offset;
_initialize_amd64obsd_tdep (void)
{
/* The OpenBSD/amd64 native dependent code makes this assumption. */
- gdb_assert (ARRAY_SIZE (amd64obsd_r_reg_offset) == X86_64_NUM_GREGS);
+ gdb_assert (ARRAY_SIZE (amd64obsd_r_reg_offset) == AMD64_NUM_GREGS);
gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64,
GDB_OSABI_OPENBSD_ELF, amd64obsd_init_abi);
void
supply_fpregset (elf_fpregset_t *fpregsetp)
{
- x86_64_supply_fxsave (current_regcache, -1, fpregsetp);
+ amd64_supply_fxsave (current_regcache, -1, fpregsetp);
}
/* Fill register REGNUM (if it is a floating-point or SSE register) in
void
fill_fpregset (elf_fpregset_t *fpregsetp, int regnum)
{
- x86_64_fill_fxsave ((char *) fpregsetp, regnum);
+ amd64_fill_fxsave ((char *) fpregsetp, regnum);
}
/* Fetch all floating-point registers from process/thread TID and store
{
int i;
- for (i = 0; i < X86_64_NUM_GREGS; i++)
+ for (i = 0; i < AMD64_NUM_GREGS; i++)
supply_register (i, regp + (user_to_gdb_regmap[i] * 8));
}
{
int i;
- for (i = 0; i < X86_64_NUM_GREGS; i++)
+ for (i = 0; i < AMD64_NUM_GREGS; i++)
if (regno == -1 || regno == i)
regcache_collect (i, regp + (user_to_gdb_regmap[i] * 8));
}
if (core_reg_size != 512)
warning ("Wrong size XMM register set in core file.");
else
- x86_64_supply_fxsave (current_regcache, -1, core_reg_sect);
+ amd64_supply_fxsave (current_regcache, -1, core_reg_sect);
break;
default:
amd64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- x86_64_init_abi (info, gdbarch);
+ amd64_init_abi (info, gdbarch);
set_gdbarch_pc_in_sigtramp (gdbarch, amd64_linux_pc_in_sigtramp);
/* Note that the AMD64 architecture was previously known as x86-64.
The latter is (forever) engraved into the canonical system name as
- returned bu config.guess, and used as the name for the AMD64 port
+ returned by config.guess, and used as the name for the AMD64 port
of GNU/Linux. The BSD's have renamed their ports to amd64; they
don't like to shout. For GDB we prefer the amd64_-prefix over the
x86_64_-prefix since it's so much easier to type. */
static int amd64_dwarf_regmap[] =
{
/* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
- X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, 2, 1,
- 4, X86_64_RDI_REGNUM,
+ AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
+ AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
+ AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
/* Frame Pointer Register RBP. */
- X86_64_RBP_REGNUM,
+ AMD64_RBP_REGNUM,
/* Stack Pointer Register RSP. */
- X86_64_RSP_REGNUM,
+ AMD64_RSP_REGNUM,
/* Extended Integer Registers 8 - 15. */
8, 9, 10, 11, 12, 13, 14, 15,
/* Return Address RA. Mapped to RIP. */
- X86_64_RIP_REGNUM,
+ AMD64_RIP_REGNUM,
/* SSE Registers 0 - 7. */
- X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
- X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
- X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
- X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
+ AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
+ AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
+ AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
+ AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
/* Extended SSE Registers 8 - 15. */
- X86_64_XMM0_REGNUM + 8, X86_64_XMM0_REGNUM + 9,
- X86_64_XMM0_REGNUM + 10, X86_64_XMM0_REGNUM + 11,
- X86_64_XMM0_REGNUM + 12, X86_64_XMM0_REGNUM + 13,
- X86_64_XMM0_REGNUM + 14, X86_64_XMM0_REGNUM + 15,
+ AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
+ AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
+ AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
+ AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
/* Floating Point Registers 0-7. */
- X86_64_ST0_REGNUM + 0, X86_64_ST0_REGNUM + 1,
- X86_64_ST0_REGNUM + 2, X86_64_ST0_REGNUM + 3,
- X86_64_ST0_REGNUM + 4, X86_64_ST0_REGNUM + 5,
- X86_64_ST0_REGNUM + 6, X86_64_ST0_REGNUM + 7
+ AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
+ AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
+ AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
+ AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7
};
static const int amd64_dwarf_regmap_len =
{
enum amd64_reg_class class[2];
int len = TYPE_LENGTH (type);
- static int integer_regnum[] = { X86_64_RAX_REGNUM, X86_64_RDX_REGNUM };
- static int sse_regnum[] = { X86_64_XMM0_REGNUM, X86_64_XMM1_REGNUM };
+ static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
+ static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
int integer_reg = 0;
int sse_reg = 0;
int i;
case AMD64_X87:
/* 6. If the class is X87, the value is returned on the X87
stack in %st0 as 80-bit x87 number. */
- regnum = X86_64_ST0_REGNUM;
+ regnum = AMD64_ST0_REGNUM;
if (writebuf)
i387_return_value (gdbarch, regcache);
break;
/* 7. If the class is X87UP, the value is returned together
with the previous X87 value in %st0. */
gdb_assert (i > 0 && class[0] == AMD64_X87);
- regnum = X86_64_ST0_REGNUM;
+ regnum = AMD64_ST0_REGNUM;
offset = 8;
len = 2;
break;
{
static int integer_regnum[] =
{
- X86_64_RDI_REGNUM, 4, /* %rdi, %rsi */
- X86_64_RDX_REGNUM, 2, /* %rdx, %rcx */
- 8, 9 /* %r8, %r9 */
+ AMD64_RDI_REGNUM, /* %rdi */
+ AMD64_RSI_REGNUM, /* %rsi */
+ AMD64_RDX_REGNUM, /* %rdx */
+ AMD64_RCX_REGNUM, /* %rcx */
+ 8, /* %r8 */
+ 9 /* %r9 */
};
static int sse_regnum[] =
{
/* %xmm0 ... %xmm7 */
- X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
- X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
- X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
- X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
+ AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
+ AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
+ AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
+ AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
};
struct value **stack_args = alloca (nargs * sizeof (struct value *));
int num_stack_args = 0;
varargs or stdargs (prototype-less calls or calls to functions
containing ellipsis (...) in the declaration) %al is used as
hidden argument to specify the number of SSE registers used. */
- regcache_raw_write_unsigned (regcache, X86_64_RAX_REGNUM, sse_reg);
+ regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
return sp;
}
if (struct_return)
{
store_unsigned_integer (buf, 8, struct_addr);
- regcache_cooked_write (regcache, X86_64_RDI_REGNUM, buf);
+ regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
}
/* Store return address. */
/* Finally, update the stack pointer... */
store_unsigned_integer (buf, 8, sp);
- regcache_cooked_write (regcache, X86_64_RSP_REGNUM, buf);
+ regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
/* ...and fake a frame pointer. */
- regcache_cooked_write (regcache, X86_64_RBP_REGNUM, buf);
+ regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
return sp + 16;
}
\f
/* The maximum number of saved registers. This should include %rip. */
-#define AMD64_NUM_SAVED_REGS X86_64_NUM_GREGS
+#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
struct amd64_frame_cache
{
{
/* Take into account that we've executed the `pushq %rbp' that
starts this instruction sequence. */
- cache->saved_regs[X86_64_RBP_REGNUM] = 0;
+ cache->saved_regs[AMD64_RBP_REGNUM] = 0;
cache->sp_offset += 8;
/* If that's all, return now. */
frame by looking at the stack pointer. For truly "frameless"
functions this might work too. */
- frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
+ frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
}
else
{
- frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
+ frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 8);
}
/* For normal frames, %rip is stored at 8(%rbp). If we don't have a
frame we find it at the same offset from the reconstructed base
address. */
- cache->saved_regs[X86_64_RIP_REGNUM] = 8;
+ cache->saved_regs[AMD64_RIP_REGNUM] = 8;
/* Adjust all the saved registers such that they contain addresses
instead of offsets. */
cache = amd64_alloc_frame_cache ();
- frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
+ frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 8) - 8;
addr = tdep->sigcontext_addr (next_frame);
char buf[8];
CORE_ADDR fp;
- frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
+ frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
fp = extract_unsigned_integer (buf, 8);
return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
const struct gdbarch_tdep *tdep = regset->descr;
gdb_assert (len == tdep->sizeof_fpregset);
- x86_64_supply_fxsave (regcache, regnum, fpregs);
+ amd64_supply_fxsave (regcache, regnum, fpregs);
}
/* Return the appropriate register set for the core section identified
\f
void
-x86_64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
+amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
/* AMD64 has an FPU and 16 SSE registers. */
- tdep->st0_regnum = X86_64_ST0_REGNUM;
+ tdep->st0_regnum = AMD64_ST0_REGNUM;
tdep->num_xmm_regs = 16;
/* This is what all the fuss is about. */
set_gdbarch_register_type (gdbarch, amd64_register_type);
/* Register numbers of various important registers. */
- set_gdbarch_sp_regnum (gdbarch, X86_64_RSP_REGNUM); /* %rsp */
- set_gdbarch_pc_regnum (gdbarch, X86_64_RIP_REGNUM); /* %rip */
- set_gdbarch_ps_regnum (gdbarch, X86_64_EFLAGS_REGNUM); /* %eflags */
- set_gdbarch_fp0_regnum (gdbarch, X86_64_ST0_REGNUM); /* %st(0) */
+ set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
+ set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
+ set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
+ set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
/* The "default" register numbering scheme for AMD64 is referred to
as the "DWARF Register Number Mapping" in the System V psABI.
}
\f
-#define I387_ST0_REGNUM X86_64_ST0_REGNUM
+#define I387_ST0_REGNUM AMD64_ST0_REGNUM
/* The 64-bit FXSAVE format differs from the 32-bit format in the
sense that the instruction pointer and data pointer are simply
reserved bits in *FXSAVE. */
void
-x86_64_supply_fxsave (struct regcache *regcache, int regnum,
+amd64_supply_fxsave (struct regcache *regcache, int regnum,
const void *fxsave)
{
i387_supply_fxsave (regcache, regnum, fxsave);
reserved bits in *FXSAVE. */
void
-x86_64_fill_fxsave (char *fxsave, int regnum)
+amd64_fill_fxsave (char *fxsave, int regnum)
{
i387_fill_fxsave (fxsave, regnum);
-/* Target-dependent code for the x86-64.
+/* Target-dependent definitions for AMD64.
Copyright 2001, 2003, 2004 Free Software Foundation, Inc.
Contributed by Jiri Smid, SuSE Labs.
/* Register numbers of various important registers. */
-#define X86_64_RAX_REGNUM 0 /* %rax */
-#define X86_64_RDX_REGNUM 3 /* %rdx */
-#define X86_64_RDI_REGNUM 5 /* %rdi */
-#define X86_64_RBP_REGNUM 6 /* %rbp */
-#define X86_64_RSP_REGNUM 7 /* %rsp */
-#define X86_64_RIP_REGNUM 16 /* %rip */
-#define X86_64_EFLAGS_REGNUM 17 /* %eflags */
-#define X86_64_ST0_REGNUM 24 /* %st0 */
-#define X86_64_XMM0_REGNUM 40 /* %xmm0 */
-#define X86_64_XMM1_REGNUM 41 /* %xmm1 */
+enum amd64_regnum
+{
+ AMD64_RAX_REGNUM, /* %rax */
+ AMD64_RBX_REGNUM, /* %rbx */
+ AMD64_RCX_REGNUM, /* %rcx */
+ AMD64_RDX_REGNUM, /* %rdx */
+ AMD64_RSI_REGNUM, /* %rsi */
+ AMD64_RDI_REGNUM, /* %rdi */
+ AMD64_RBP_REGNUM, /* %rbp */
+ AMD64_RSP_REGNUM, /* %rsp */
+ AMD64_R8_REGNUM = 8, /* %r8 */
+ AMD64_R15_REGNUM = 15, /* %r15 */
+ AMD64_RIP_REGNUM, /* %rip */
+ AMD64_EFLAGS_REGNUM, /* %eflags */
+ AMD64_ST0_REGNUM = 24, /* %st0 */
+ AMD64_XMM0_REGNUM = 40, /* %xmm0 */
+ AMD64_XMM1_REGNUM /* %xmm1 */
+};
/* Number of general purpose registers. */
-#define X86_64_NUM_GREGS 24
+#define AMD64_NUM_GREGS 24
-void x86_64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch);
+extern void amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch);
/* Fill register REGNUM in REGCACHE with the appropriate
floating-point or SSE register value from *FXSAVE. If REGNUM is
-1, do this for all registers. This function masks off any of the
reserved bits in *FXSAVE. */
-extern void x86_64_supply_fxsave (struct regcache *regcache, int regnum,
- const void *fxsave);
+extern void amd64_supply_fxsave (struct regcache *regcache, int regnum,
+ const void *fxsave);
/* Fill register REGNUM (if it is a floating-point or SSE register) in
*FXSAVE with the value in GDB's register cache. If REGNUM is -1, do
this for all registers. This function doesn't touch any of the
reserved bits in *FXSAVE. */
-void x86_64_fill_fxsave (char *fxsave, int regnum);
+extern void amd64_fill_fxsave (char *fxsave, int regnum);
\f
/* Variables exported from amd64nbsd-tdep.c. */
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